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| Rev. 1.0, Jun. 2010 K5N1229ACD-BQ12 MCP Specification 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash + 128Mb (8M x16) Multiplexed Synchronous Burst UtRAM2 datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2009 Samsung Electronics Co., Ltd. All rights reserved. -1- K5N1229ACD-BQ12 datasheet History Draft Date Jun. 1, 2010 Rev. 1.0 MCP Memory Revision History Revision No. 0.0 Remark Preliminary Editor H.Y.Min Initial issue. - 512M Bit SLC Mux NOR Flash C-die_Ver 1.0 - 128M Bit Mux UtRAM2 C-die_Ver 1.0 1.0 Jun. 22, 2010 Final H.Y.Min -2- K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 1. Features * This device has the Sync MRS option only (Extended Configuration Register) * Single Voltage, 1.7V to 1.95V for Read and Write operations * Organization - 33,554,432 x 16 bit ( Word Mode Only) * Multiplexed Data and Address for reduction of interconnections - A/DQ0 ~ A/DQ15 * Read While Program/Erase Operation * Multiple Bank Architecture - 16 Banks (32Mb Partition) * OTP Block : Extra 512-Word block * Read Access Time (@ CL=30pF) - Asynchronous Random Access Time : 100ns - Synchronous Random Access Time :95ns - Burst Access Time :7ns (108MHz) * Burst Length : - Continuous Linear Burst - Linear Burst : 8-word & 16-word with Wrap * Block Architecture - Uniform block part : Five hundred twelve 64Kword blocks - Boot block part : Four 16Kword blocks and five hundred eleven 64Kword blocks (Bank 0 contains four 16 Kword blocks and thirty-one 64Kword blocks, Bank 1 ~ Bank 15 contain four hundred eighty 64Kword blocks) * Reduce program time using the VPP * Support 512-word Buffer Program * Power Consumption (Typical value, CL=30pF) - Synchronous Read Current : 35mA at 133MHz - Program/Erase Current : 25mA - Read While Program/Erase Current : 45mA - Standby Mode/Auto Sleep Mode : 30uA * Block Protection/Unprotection - Using the software command sequence - Last two boot blocks are protected by WP=VIL (Boot block part) - Last one block (BA511) is protected by WP=VIL (Uniform block part) - All blocks are protected by VPP=VIL * Handshaking Feature - Provides host system with minimum latency by monitoring RDY * Erase Suspend/Resume * Program Suspend/Resume * Unlock Bypass Program/Erase * Blank Check Feature * Hardware Reset (RESET) * Data Polling and Toggle Bits - Provides a software method of detecting the status of program or erase completion * Endurance - 100K Program/Erase cycles * Support Common Flash Memory Interface * Low Vcc Write Inhibit * Output Driver Control by Configuration Register -3- K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 2. General Description The K5N1229ACD is a Multi Chip Package Memory which combines 512Mb SLC MuxNOR Flash Memory and 128Mb Multiplexed Synchronous Burst Uni-Transistor Random Access Memory2. The 512Mb Muxed NOR Flash featuring single 1.8V power supply is a 512Mbit Muxed Burst Multi Bank Flash Memory organized as 32Mx16. The memory architecture of the device is designed to divide its memory arrays into 512blocks(Uniform block part)/515 blocks(Boot block part) with independent hardware protection. This block architecture provides highly flexible erase and program capability. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Regarding read access time, the device(for 66/83MHz) provides an 11ns burst access time and an 95ns initial access time at 66MHz. At 83MHz, the device(for 66/83MHz) provides an 9ns burst access time and an 95ns initial access time. At 108MHz, the device(for 108/133MHz) provides an 7ns burst access time and an 95ns initial access time. At 133MHz, the device(for 108/133MHz) provides an 6ns burst access time and an 95ns initial access time. The device performs a program operation in units of 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.6sec. The device requires 25mA as program/erase current in the extended temperature ranges. SAMSUNG's UtRAM products are designed to meet the request from the customers who want to cope with the fast growing mobile applications that need high-speed random access memory. UtRAM is the solution for the mobile market with its low cost, high density and high performance feature. device is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous operation (asynchronous read and asynchronous write), the fully synchronous operation (synchronous burst read and synchronous burst write). These operation modes are defined through the configuration register setting. It supports the special features for the standby power saving. Those are the PAR(Partial Array Refresh) mode, and internal TCSR(Temperature Compensated Self Refresh). It also supports variable and fixed latency, driver strength settings, Burst sequence (wrap or No-wrap) options and a device ID register (DIDR). The K5N1229ACD is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 56-ball FBGA Type. -4- K5N1229ACD-BQ12 datasheet 3 4 5 6 7 8 9 10 11 Rev. 1.0 MCP Memory 3. Pin Configuration 1 2 12 13 14 A NC - - - - - - - - - - - - NC B - - - - - - - - - - - - - - C - - NC DNU - - /LBc /UBc - - A24r NC - - D - - RDYr /WAITc A21rc VSSrc CLKrc VCCrc /WErc VPPr A19rc A17rc A22rc - - E - - VCCQrc A16rc A20rc /AVDrc A23r /RESETr /WPr A18rc /CEr VSSQrc - - F - - VSSrc ADQ7rc ADQ6rc ADQ13rc ADQ12rc ADQ3rc ADQ2rc ADQ9rc ADQ8rc /OErc - - G - - ADQ15rc ADQ14rc VSSQrc ADQ5rc ADQ4rc ADQ11rc ADQ10rc VCCQrc ADQ1rc ADQ0rc - - H - - NC VCCrc - - /CSc CREc - - DNU NC - - J - - - - - - - - - - - - - - K NC - - - - - - - - - - - - NC 56 FBGA: Top View (Ball Down) NOR + UtRAM NOR Flash UtRAM2 Power Ground NC/DNU -5- K5N1229ACD-BQ12 datasheet Pin Function(NOR Flash) Pin Name ADQ0rc ~ ADQ15rc A16rc ~ A22rc CLKrc /OErc /WErc /AVDrc Rev. 1.0 MCP Memory 4. Pin Description Pin Name A23r, A24r /CEr /WPr /RESETr VPPr Pin Name /LBc,/UBc CREc /CSc Pin Function(Common) Multiplexed Address/Data Input/Output Address Input Clock Output Enable Write Enable Address Valid Input Ready Out(NOR) Data Availability (UtRAM) Power Supply Data Input/Output Power Ground Pin Function Do Not Use No Connection Address Input(NOR only) Chip Enable Write Enable Hardware Reset Accelerates Programming Pin Function(UtRAM2) Lower Byte Enable, Upper Byte Enable Control Register Enable Chip Enable RDYr /WAITc VCCrc VCCQrc VSSrc Pin Name DNU NC -6- K5N1229ACD-BQ12 datasheet K5 N 12 29 A C D-B Q 12 Rev. 1.0 MCP Memory 5. Ordering Information Samsung MCP Memory 2Chip MCP UtRAM2 Access Time 12 : 108MHz Device Type N : Muxed NOR + Muxed UtRAM2 Flash Access Time Q : 108MHz NOR Flash Density 12 : 512Mb, x16 Package B : FBGA(HF, OSP LF) Version D : 5rd Generation Block Architecture C :Uniform Boot Block UtRAM2 Density, (Organization) 29 : 128Mb, x16,(Ut2) Operating Voltage A : 1.8V/1.8V -7- K5N1229ACD-BQ12 datasheet VSSrc VCCrc VCCQrc Rev. 1.0 MCP Memory 6. Functional Block Diagram Address(A16rc to A22rc) Address(A23r,A24r) CLKrc /OErc /WErc /AVDrc RDYr,/WAITc /CEr /WPr /RESETr VPPr 512Mb NOR Flash Memory VSSrc VCCrc VCCQrc ADQ0rc to ADQ15rc 128Mb UtRAM2 /CSc /LBc,/UBc CREc -8- K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 7. Package Dimension 56-Ball Fine pitch Ball Grid Array Package (measured in millimeters) 0.08 MAX Units:millimeters #A1 INDEX MARK 8.000.10 0.50 x 13 = 6.50 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Datum A) 8.000.10 A B #A1 (Datum B) A B 2.25 9.200.10 E F G H J K 0.230.05 1.100.10 1.00 0.50 3.25 1.00 56-0.300.05 0.20 M A B TOP VIEW BOTTOM VIEW -9- 9.200.10 D 0.50 x 9 = 4.50 C K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 512Mb (32M x16) Mux NOR Flash C-die - 10 - K5N1229ACD-BQ12 datasheet Bank 0 Address X Dec Bank 0 Cell Array Rev. 1.0 MCP Memory 1.0 FUNCTIONAL BLOCK DIAGRAM Vcc Vss Vpp CLK CE OE WE WP RESET RDY AVD I/O Interface & Bank Control Bank 1 Address X Dec Latch & Control Y Dec Y Dec Bank 1 Cell Array Latch & Control Bank 15 Address X Dec Bank 15 Cell Array Y Dec A16~A24 A/DQ0~ A/DQ15 Erase Control Block Inform Program Control Latch & Control High Voltage Gen. [Table 1] PRODUCT LINE-UP Mode Speed Option Max. Initial Access Time (tIAA, ns) Max. Burst Access Time (tBA, ns) Max. Access Time (tAA, ns) Asynchronous Max. CE Access Time (tCE, ns) Max. OE Access Time (tOE, ns) 1C (66MHz) 95 11 100 100 15 1D (83MHz) 95 9 100 100 15 1E (108MHz) 95 7 100 100 15 1F (133MHz) 95 6 100 100 15 Synchronous/Burst VCC=1.7V -1.95V - 11 - K5N1229ACD-BQ12 datasheet Bank 0 ~ Bank 15 Block Sizes Rev. 1.0 MCP Memory [Table 2] DEVICE BANK DIVISIONS Type 512Mbit (Boot block part) 512Mbit (Uniform block part) [Table 3] DEVICE BANK DIVISIONS (Uniform block) Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bank size 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb Quantity of Blocks 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Block Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Four 16Kword blocks and five hundred eleven 64Kword blocks Five hundred twelve 64Kword blocks [Table 4] DEVICE BANK DIVISIONS (Top Boot block) Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bank size 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb Quantity of Blocks 4 31 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Block Size 16 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords - 12 - K5N1229ACD-BQ12 datasheet Bank size 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb 32Mb Quantity of Blocks 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 31 4 Rev. 1.0 MCP Memory Block Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 16 Kwords [Table 5] DEVICE BANK DIVISIONS (Bottom Boot block) Bank 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - 13 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 2.0 PRODUCT INTRODUCTION The device is an 512Mbit (536,870,912 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 512 blocks (64-Kword x 512 blocks, Uniform block part) / 515 blocks (16-Kword x 4 + 64-Kword x 511, Boot block part). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 512 / 515 memory blocks can be hardware protected. Regarding read access time, at 66MHz, the device(for 66/83MHz) provides a burst access of 11ns with initial access times of 95ns at 30pF. At 83MHz, the device(for 66/83MHz) provides a burst access of 9ns with initial access times of 95ns at 30pF. At 108MHz, the device(for 108/133MHz) provides a burst access of 7ns with initial access times of 95ns at 30pF. At 133MHz, the device(for 108/133MHz) provides a burst access of 6ns with initial access times of 95ns at 30pF. The command set of device is compatible with standard Flash devices. The device uses Chip Enable (CE), Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The device is implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The device has means to indicate the status of completion of program/erase operations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only 35mA as burst and asynchronous mode read current and 25mA for Buffer program/erase operations. [Table 6] Device Bus Operations Operation Asynchronous Read Operation Write Standby Hardware Reset Load Initial Burst Address CE L L H X L L H X L OE L H X X H L X X H WE H L X X H H X X H A16-24 Add In Add In X X Add In X X X Add In A/DQ0-15 Add In/DOUT Add In / DIN High-Z High-Z Add In Burst DOUT High-Z High-Z Add In RESET H H H L H H H L H X X H X X CLK L L X X X X AVD Burst Read Operation Terminate Burst Read Cycle Terminate Burst Read Cycle via RESET Terminate Current Burst Read Cycle and Start New Burst Read Cycle NOTE : L=VIL (Low), H=VIH (High), X=Don't Care. - 14 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 3.0 COMMAND DEFINITIONS The device operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 8. [Table 7] Command Sequences Command Definitions Asynchronous Read Reset5),20) Autoselect Manufacturer ID6) Autoselect Device ID6) Autoselect Block Protection Verify7) Autoselect Handshaking 6), 8) Program Unlock Bypass Unlock Bypass Program 9) Unlock Bypass Block Erase9) Unlock Bypass Chip Erase9) Unlock Bypass Reset Chip Erase Block Erase Erase Suspend 10) Erase Resume11) Program Suspend 12) Program Resume 11) Block Protection/Unprotection 13) CFI Query 14) Blank check Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Cycle 1 1 4 4 4 4 4 3 2 2 2 2 6 6 1 1 1 1 3 1 4 1st Cycle RA RD XXXH F0H 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH XXX A0H XXX 80H XXXH 80H XXXH 90H 555H AAH 555H AAH (DA)XXXH B0H (DA)XXXH 30H (DA)XXXH B0H (DA)XXXH 30H XXX 60H (DA)X55H 98H 555H AAH 2AAH 55H BA BCH BA D0H XXX 60H ABP 60H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H PA PD BA 30H XXXH 10H XXXH 00H 2AAH 55H 2AAH 55H 555H 80H 555H 80H 555H AAH 555H AAH 2AAH 55H 2AAH 55H 555H 10H BA 30H (DA)555H 90H (DA)555H 90H (BA)555H 90H (DA)555H 90H 555H A0H 555H 20H (DA)X00H ECH (DA)X01H NOTE6 (BA)X02H 00H / 01H (DA)X03H 0H/1H PA PD 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle - 15 - K5N1229ACD-BQ12 datasheet Cycle Add Data Add Data Add Data Add Data Add Data Add Data Add Data 3 1 3 3 3 3 4 1st Cycle 555H AAH BA 29H 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H XXX F0H NOTE 18 C0H NOTE 19 C5H XXX 70H 555H 75H XXX 00H 2nd Cycle 2AAH 55H 3rd Cycle BA 25H BA WC Rev. 1.0 MCP Memory 4th Cycle 5th Cycle PA PD 6th Cycle WBL PD Command Definitions Write to Buffer 15) Program buffer to Flash 15) Write to Buffer Abort Reset 16),20) Set Burst Mode Configuration Register 17),18) Set Extended Configuration Register 17),19) Enter OTP Block Region Exit OTP Block Region NOTE : 1) RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A24 ~ A14), DA : Bank Address (A24 ~ A21) ABP : Address of the block to be protected or unprotected , DI :Die revision ID, CR : Configuration Register Setting, WBL : Write Buffer Location, WC : Word Count 2) The 4th cycle data of autoselect mode and RD are output data. The others are input data. 3) Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WC and Device ID. 4) Unless otherwise noted, address bits A24-A11 are don't cares. 5) The reset command is required to return to read mode. If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode. If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode. If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that bank was in erase suspend mode. 6) The 3rd and 4th cycle bank address of autoselect mode must be same. Device ID Data : Top(3010H), Bottom(3011H), Uniform(3012H) 7) Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block. OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked. 8) 0H for handshaking, 1H for non-handshaking 9) The unlock bypass command sequence is required prior to this command sequence. 10) The system may read and program in non-erasing blocks when in the erase suspend mode. The system may enter the autoselect mode when in the erase suspend mode. The erase suspend command is valid only during a block erase operation, and requires the bank address. 11) The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address. 12) This mode is used only to enable Data Read by suspending the Program operation. 13) Set ABP(Address of the block to be protected or unprotected) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected. 14) Command is valid when the device is in Read mode or Autoselect mode. 15) For Buffer Program, Firstly Enter "Write to Buffer" Command sequence and then Enter Block Address and Word Count which is the number of word data will be programmed. Word Count is smaller than the number of data wanted to program by one, Example if 15 words are wanted to program then WC (Word Count) is 14. After Entering Command, Enter PA/PD's (Program Addresses/ Program Data). Finally Enter "Program buffer to Flash" Command sequence, This starts a buffer program operation. This Device supports 512-word Buffer Program. There is some caution points. - The number of PA/PD's which are entered must be same to WC+1 - PA's which are entered must be same A24~A9 address bits because Buffer Address is A24~A9 address and decided by PA entered firstly. - If PA which are entered isn't same Buffer Address, then PA/PD which is entered may be ignored and this buffer programming operation is aborted. To return to normal operation, hardware reset or "Write to Buffer Abort Reset" command is issued. - Overwrite for program buffer is also prohibited. 16) Command sequence resets device for next command after aborted write-to-buffer operation. 17) See "Set Burst Mode Configuration Register" for details. 18) On the third cycle, the data should be "C0h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched. 19) On the third cycle, the data should be "C5h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched. 20) After software reset and write to buffer abort reset command, min. 5us recovery time is needed for normal read mode. - 16 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.0 DEVICE OPERATION The device has inputs/outputs that accept both address and data information. To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the system must drive CLK, AVD and CE to VIL and OE to VIH when providing an address to the device, and drive CLK, WE and CE to VIL and OE to VIH when writing commands or data. The device provides the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the entire device can be erased. Table 17 indicates the address space that each block occupies. The device's address space is divided into sixteen banks. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "block address" is the address bits required to uniquely select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. 4.1 Read Mode The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode. Sync MRS option (Extended Configuration Register) The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register Setting to A13=0, A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK. 4.1.1. Asynchronous Read Mode For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A24, while driving CLK and AVD and CE to VIL. WE and OE should remain at VIH. Note that CLK must remain low for asynchronous read mode. The address is latched at the rising edge of AVD, and then the system can drive OE to VIL. The data will appear on A/DQ0-A/DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. The asynchronous access time is measured from a valid address, falling edge of AVD or falling edge of CE whichever occurs last. To prevent the memory content from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. 4.1.2. Synchronous (Burst) Read Mode The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should determine how many clock cycles are desired for the initial word(tIAA) of each burst access and what mode of burst operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be read by synchronous read mode with a bank address which is programming or erasing. This status data by synchronous read mode can be output and sustained until the system asserts CE high or RESET low or AVD low in conjunction with a new address. To initiate the synchro nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the pro gram or erase operation. 4.1.2.1 . Continuous Linear Burst Read Sync MRS option (Extended Configuration Register) The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register Setting to A13=0, A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK. The initial word is output tIAA after the rising edge of the last CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of additional clock cycle can vary from zero to thirteen cycles, and the exact number of additional clock cycle depends on not olny the starting address of burst read but also programmable wait state setting. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the system asserts CE high or RESET low or AVD low in conjunction with a new address.(See Table 7.) The reset command does not terminate the burst read operation. When it accesses the bank is programming or erasing, continuous burst read mode will output status data. And status data will be sustained until the system asserts CE high or RESET low or AVD low in conjunction with a new address. Note that at least 10ns is needed to start next burst read operation from terminating previous burst read operation in the case of asserting CE high. - 17 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 8-, 16-Word Linear Burst Read As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap mode, in which a fixed number of words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode.(See Table. 9) [Table 8] Burst Address Groups(Wrap mode only) Burst Mode 8 word 16 word Group Size 8 words 16 words Group Address Ranges 0-7h, 8-Fh, 10-17h, .... 0-Fh, 10-1Fh, 20-2Fh, .... As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar manner, 16-word wrap mode begins its burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. 4.2 Programmable Wait State The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven from low to high for burst read mode. Upon power up, the number of total initial access cycles defaults to fourteen. 4.3 Handshaking The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates the initial word of valid burst data. (RDY can be low active by Extended configuration register A11 settng : RDY low indicates data valid) Using the autoselect command sequence, the handshaking feature will be verified in the device. 4.4 Set Burst Mode Configuration Register The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode configuration register must be set before the device enters burst mode. The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h, address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched. The device returns to default setting after power up or hardware reset. 4.4.1. Programmable Wait State Configuration This feature informs the device the number of clock cycles that must elapse after AVD is driven from low to high before data will be available. This value is determined by the input frequency of the device. Address bits A14-A11 determine the setting. (See Configuration Register table 10.) The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will revert the wait state to the default setting, that is 14 initial cycles. 4.4.2. Burst Read Mode Setting The device supports three different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap. - 18 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.4.3. RDY Configuration By default, the RDY pin will be high whenever there is valid data on the output. (RDY can be low active by Extended configuration register A11 settng : RDY low indicates data valid) The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting. The RDY pin behaves same way in word boundary crossing case. [Table 9] Burst Mode Configuration Register Table Address Bit A21 A20 Output Driver Control A19 Function 000 = setting 0 001 = setting 1 010 = setting 2 (Reserve) 011 = setting 3 (Reserve) 100 = setting 4 (default) 101 = setting 5 (Reserve) 110 = setting 6 (Reserve) 111 = setting 7 0 = RDY active with data(default) 1 = RDY active one clock cycle before data 000 = Continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011 ~ 111 = Reserve 0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH 0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*) 0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*) 0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*) 0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*) 0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*) 0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*) 0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*) 1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*) 1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default) 1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH 1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH 1100 ~1111 = Reserve Settings(Binary) A18 A17 A16 A15 A14 A13 A12 RDY Active Burst Read Mode Programmable Wait State A11 NOTE : Initial wait state should be set according to it's clock frequency. Table 10 recommend the program wait state for each clock frequencies. Not 100% tested [Table 10] Extended Configuration Register Table Address Bit A13 A12 A11 Read Mode Function 00 = Asynchronous Read Mode(default) 01 = Synchronous Burst Read Mode 10 ~ 11 = Reserve 0 = RDY signal is active high (default) 1 = RDY signal is active low Settings(Binary) RDY Polarity NOTE : Default mode is asynchronous read mode. (A13=0, A12=0) In this mode device is still in asynchronous read even if it is in CLK rising while AVD low condition. To use synchronous read mode, user should set Extended Configuration Register (A13=0, A12=1). In this mode both of asynchronous and synchronous read mode is available. The synchronous(burst) mode should be started on the last rising edge of the CLK input while AVD is held low after Extended Mode Register Setting to A13=0, A12=1. [Table 11] Burst Address Sequences Start Addr. 0 1 Wrap 2 . . Burst Address Sequence Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... . . 8-word Burst 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 . . 16-word Burst 0-1-2-3 ... -D-E-F 1-2-3-4 ... -E-F-0 2-3-4-5 ... -F-0-1 . . - 19 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.5 Output Driver Setting The device supports four kinds of output driver setting for matching the system chracteristics. The users can tune the output driver impedance of the data and RDY outputs by address bits A21-A19. (See Configuration Register Table) Table 13 shows which output driver would be tuned and the strength according to A21-A19. Upon power-up or reset, the register will revert to the default setting. [Table 12] Output Driver setting Table Address Bits Value 000 001 010 A21-A19 011 100 101 110 111 Function Driver Multiplier : 1/3 Driver Multiplier : 1/2 Reserve Reserve Driver Multiplier : 1 (default) Reserve Reserve Driver Multiplier : 1.5 4.6 Autoselect Mode By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection. Table 14 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write Reset command(F0H) into the command register. [Table 13] Autoselect Mode Description Description Manufacturer ID Device ID Block Protection/Unprotection Handshaking Address (DA) + 00H (DA) + 01H (BA) + 02H (DA) + 03H Read Data ECH Top boot(3010H), Bottom boot(3011H), Uniform block(3012H) 01H (protected), 00H (unprotected) 0H : handshaking, 1H : non-handshaking 4.7 Standby Mode When the CE inputs is held at VCC 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE input. When the device is in either of these standby modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specification. 4.8 Automatic Sleep Mode The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses remain stable for tAA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and OE signal, so CE, WE and OE signals are held at any state. In a sleep mode, output data is latched and always available to the system. When OE is active, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current. 4.9 Output Disable Mode When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state. - 20 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.10 Block Protection & Unprotection To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are don't care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command). The device offers three types of data protection at the block level: * The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block. * When WP is at VIL, the two outermost blocks are protected.(Boot block part) * When WP is at VIL, the last one block (BA511) is protected.(Uniform block part) * When VPP is at VIL, all blocks are protected. Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL. 4.11 Hardware Reset The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 12 for the timing diagram. When RESET is at logic high, the device is in standard operation. 4.12 Software Reset The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in Don't Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an program command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend) 4.13 Program The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. 4.14 Accelerated Program The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In accelerated program mode, the system would use a two-cycle program command sequence for only a word program. By removing VID returns the device to normal operation mode. Note that Read While Accelerated Program(Erase) and Program suspend(Erase suspend) mode are not guaranteed. * Program/Erase cycling must be limited below 100cycles for optimum performance. * Ambient temperature requirements : TA = 30C10C - 21 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.15 Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 512-word in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the block address in which programming will occur. The fourth cycle writes the block address and the number of word locations, minus one, to be programmed. For example, if the system will program 19 unique address locations, then 12h should be written to the device. This tells the device how many write buffer addresses will be loaded with data. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A24(max.) ~ A9 entered at fifth cycle. All subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit A24(max.) ~ A9 as those entered at fifth cycle. Write buffer locations may be loaded in any order. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com mand at the block address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/ resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. Note also that an address loaction cannot be loaded more than once into the write-buffer-page. The Write Buffer Programming Sequence can be aborted in the following ways: * Loading a value that is greater than the buffer size(512-word) during then number of word locations to Program step. (In case, WC > 1FFH @Table 8) * The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table 8) * Writing a Program address to have a different write-buffer-page with selected write-buffer-page ( Address bits A24(max) ~ A9 are different) * Writing non-exact "Program Buffer to Flash" command The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-Abort Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass mode. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." 4.16 Accelerated Write Buffer Programming The device provides accelerated Write Buffer Program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In accelerated Write Buffer Program mode, the system must enter "Write to Buffer" and "Program Buffer to Flash" command sequence to be same as them of normal Write Buffer Programming. Note that the third cycle of "Write to Buffer Abort Reset" command sequence is required in an accelerated mode. Note that Read While Accelerated Write Buffer Program and Program suspend mode are not guaranteed. * Program/Erase cycling must be limited below 100cycles for optimum performance. * Ambient temperature requirements : TA = 30C10C 4.17 Chip Erase To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. - 22 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.18 Block Erase To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the rising edge of AVD , while the Block Erase command is latched on the rising edge of WE. Multiple blocks can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation. The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By removing VID returns the device to normal operation mode. 4.19 Blank check The Blank Check operation is used one block at a time to check whether a block is completely erased or not. It is not available during Program Suspend or Erase Suspend. For using Blank Check, first issue the command which has 4-cycle and check the status. The Bank addressed in Blank Check Command is automatically changed to Status check mode, until Reset command (XXXH / F0H) is issued. During a blank check operation, DQ status flags indicates a busy status (DQ6, DQ2 = toggle / DQ5=0). Upon completion, the DQ status flags indicates that Blank check operation is passed (DQ6 = toggle , DQ5=1 and DQ1=1). That means the block is completely erased. In Blank check operation failure case, the DQ status flags indicates DQ6 = toggle , DQ5=1 and DQ1=0. The block is not completely erased. No other commands will be recognized except status read operation during Blank Check operation. Blank Check cannot be suspended. After the completion of the Blank Check operation, any valid command can be issued after Reset command (XXXH / F0H). NOTE that, unexpected power off or hardware reset during internal write routine may make blank check operation unavailable. And Blank check cannot be used in OTP block area. 4.20 Unlock Bypass The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase, chip erase, write to buffer and write to buffer abort reset operation.. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles, the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.). 4.21 Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is possible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 30us(recovery time) to suspend the erase operation. Therefore system must wait for 30us(recovery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from a bank which don't include the block being erased without recovery time(max. 30us) after Erase Suspend command. And, after the maximum 30us recovery time, the device is availble for programming data in a block that is not being erased. But, when the Erase Suspend command is written during the block erase time window (50us), the device terminates the block erase time window and suspends the erase operation in about 2us. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in the bank address which is operating in Erase Suspend or Erase Resume. While erase can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. - 23 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 4.22 Program Suspend / Resume The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 10us is needed to enter the Program Suspend Read mode. Therefore system must wait for 10us(recovery time) to read the data from the bank which include the block being programmed. Otherwise, system can read the data immediately from a bank which don't include block being programmed without recovery time(max.10us) after Program Suspend command. Like an Erase Suspend mode, the device can be returned to Program mode by using a Program Resume command. While program can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. In the program suspend mode, protect/unprotect command is prohibited. 4.23 Read While Write Operation The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write operation. An erase operation may also be suspended to read from or program to another location within the same bank(except the block being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current specifications. 4.24 OTP Block Region The OTP Block feature provides a 512-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 8). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (1FFFE00h~1FFFFFFh : Top Boot block device/Uniform block device, 0000000h-00001FFh : Bottom Boot block device) normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. Customer Lockable In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command seqeunce (Table 8) with an OTP Block address. The Locking operation has to be above 100us. "Exit OTP Block" commnad sequence and Hardware reset makes locking operation finished and then exiting from OTP Block after 30us. The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operations. After entering OTP block, program/erase operation on main blocks is prohibited. Enter OTP block command is not allowed while other operation is excuting. 4.25 Low VCC Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO. 4.26 Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle. 4.27 Logical Inhibit Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. - 24 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 5.0 FLASH MEMORY STATUS FLAGS The device has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being executed internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins. The status data can be read during burst read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If status read is performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3, DQ2 and DQ1. [Table 14] Hardware Sequence Flags Status Programming Block Erase or Chip Erase or Blank check Erase Suspend Read Erase Suspend Read In Progress Erase Suspend Program Program Suspend Read Program Suspend Read Programming Exceeded Time Limits Block Erase or Chip Erase or Blank check Fail Blank check Pass Erase Suspend Program Write-toBuffer3) BUSY state Exceeded Timing Limits ABORT State Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block Program Suspended Block Non- program Suspended Block DQ7 DQ7 0 1 Data DQ7 DQ7 Data DQ7 0 0 DQ7 DQ7 DQ7 DQ7 DQ6 Toggle Toggle 1 Data Toggle 1 Data Toggle Toggle Toggle Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 0 Data 1 1 1 1 0 1 0 DQ3 0 1 0 Data 0 0 Data 0 1 1 0 0 0 0 DQ2 1 Toggle Toggle1) Data 1 Toggle1) Data No Toggle (NOTE 2) (NOTE 2) No Toggle No Toggle No Toggle No Toggle DQ1 0 0 0 Data 0 0 Data 0 0 1 0 0 0 1 NOTE : 1) DQ2 will toggle when the device performs successive read operations from the erase/program suspended block. 2) If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle. 3) Note that DQ7 during Write-to-Buffer-Programming indicates the data-bar for DQ7 data for the last loaded write-buffer address location. DQ7 : Data Polling When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the block being erased or bank contains the block, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 2us and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. DQ6 : Toggle Bit Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 2us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block. #OE or #CE should be toggled in each toggle bit status read. - 25 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory DQ5 : Exceed Timing Limits If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. Also the result of blank check can be checked by DQ5=1. DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles if the bank including an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. #OE or #CE should be toggled in each toggle bit status read. DQ1 : Buffer Program Abort Indicator DQ1 indocates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-BufferAbort-Reset command sequence to return the device to reading array data. Also DQ1 will go High if the blank check is passed. DQ1 will go low in the blank check failure. RDY: Ready Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state. Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address Start Read(DQ0~DQ7) Valid Address DQ7 = Data ? No No Yes DQ6 = Toggle ? Yes No No DQ5 = 1 ? Yes DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes Read twice(DQ0~DQ7) Valid Address No DQ7 = Data ? No DQ6 = Toggle ? Yes Fail Pass Fail Pass Figure 1. Data Polling Algorithms Figure 2. Toggle Bit Algorithms - 26 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.0 Common Flash Memory Interface Common Flash Memory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H , the device enters the CFI mode. And then if the system writes the address shown in Table 16, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command. [Table 15] Common Flash Memory Interface Code Description Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0017H 0019H 0085H 0095H 0007H 000AH 000AH 0013H 0003H 0003H 0003H 0003H 001AH 0000H 0000H 000AH 0000H 0002H 0003H 0000H 0080H 0000H Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp(Acceleration Program) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Vpp(Acceleration Program) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Typical timeout per single word write 2N us Typical timeout for Max buffer write 2N us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms(00H = not supported) Max. timeout for word write 2 times typical N Max. timeout for buffer write 2 times typical N Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2 times typical(00H = not supported) N Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device1) Erase Block Region 1 Information (Boot block part) Bits 0~15: y+1=block number Bits 16~31: block size= z x 256bytes - 27 - K5N1229ACD-BQ12 datasheet Description Addresses (Word Mode) 2DH 2EH 2FH 30H 31H 32H 33H 34H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 40H 41H 42H 43H 44H 45H Rev. 1.0 MCP Memory Data 00FFH 0001H 0000H 0002H 00FEH 0001H 0000H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0050H 0052H 0049H 0031H 0031H 0000H Erase Block Region 1 Information (Uniform block part) Bits 0~15: y+1=block number Bits 16~31: block size= z x 256bytes Erase Block Region 2 Information (Boot block part) Erase Block Region 2 Information (Uniform block part) Erase Block Region 3 Information Erase Block Region 4 Information Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 00 = Not Supported, 01 = Supported Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 03 = 16 Word Page Top/Bottom Boot/Uniform Block Flag 02H = Bottom Boot Device, 03H = Top Boot Device, 04H = Uniform Device Max. Operating Clock Frequency (MHz ) 2) RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists) Handshaking 00 = Not Supported at both mode, 01 = Supported at Sync. Mode 10 = Supported at Async. Mode, 11 = Supported at both Mode NOTE : 1) Uniform block part : Data is 01H Boot block part : Data is 02H 2) Max. Operating Clock Frequency : Data is 85H in 108/133Mhz part , Data is 53H in 66/83Mhz part 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 0002H 0001H 0000H 0001H 0001H 0001H 0000H 0003H 0085H 0000H 0001H - 28 - K5N1229ACD-BQ12 datasheet Symbol Vcc Vcc VIN Tstg IOS TA Rating -0.5 to +2.5 -0.5 to +9.5 -0.5 to +2.5 -65 to +100 5 -25 to + 85 Rev. 1.0 MCP Memory 7.0 ABSOLUTE MAXIMUM RATINGS Parameter Unit Voltage on any pin relative to VSS VPP All Other Pins Storage Temperature Short Circuit Output Current Operating Temperature V C mA C NOTE : 1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns. 2) Minimum DC input voltage is -0.5V on VPP . During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +12.0V for periods <20ns. 3) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. - 29 - K5N1229ACD-BQ12 datasheet Symbol VCC VSS Min 1.7 0 Typ. 1.8 0 Max 1.95 0 Rev. 1.0 MCP Memory 8.0 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Unit V V NOTE : Voltage reference to GND 1) Data retention is not guaranteed on Operating condition Extended temperature(-25'C~85'C) over. 9.0 DC CHARACTERISTICS Parameter Input Leakage Current VPP Leakage Current Output Leakage Current Active Burst Read Current Active Asynchronous Read Current Active Write Current 2) Read While Write Current Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode 3) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage Vpp current in program/erase Symbol ILI ILIP ILO ICCB1 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH VID VLKO Ivpp VPP = 9.5V VPP = 1.95V IOL = 100 A , VCC=VCCmin IOH = -100 A , VCC=VCCmin Test Conditions VIN=VSS to VCC, VCC=VCCmax VCC=VCCmax , VPP=VCCmax VCC=VCCmax , VPP=9.5V VOUT=VSS to VCC, VCC=VCCmax, OE=VIH CE=VIL, OE=VIH (@133MHz) CE=VIL, OE=VIH CE=VIL, OE=VIH, WE=VIL, VPP=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH , VPP=9.5V CE= RESET=VCC 0.2V RESET = VSS 0.2V CE=VSS 0.2V, Other Pins=VIL or VIH VIL = VSS 0.2V, VIH = VCC 0.2V 10MHz Min - 1.0 - 1.0 - 1.0 -0.5 VCC-0.4 VCC-0.1 8.5 Typ 35 35 25 45 20 30 30 30 9.0 0.8 Max + 1.0 + 1.0 35 + 1.0 55 55 40 70 30 120 120 120 0.4 VCC+0.4 0.1 9.5 1.4 5 50 Unit A A A A mA mA mA mA mA A A A V V V V V V mA A NOTE : 1) Maximum ICC specifications are tested with VCC = VCCmax. 2) ICC active while Internal Erase or Internal Program is in progress. 3) Device enters automatic sleep mode when addresses are stable for tAA + 60ns. - 30 - K5N1229ACD-BQ12 datasheet Symbol tVCS tRH All Speed Options Min 200 200 Rev. 1.0 MCP Memory 10.0 VCC POWER-UP Parameter Vcc Setup Time Time between RESET (high) and CE (low) NOTE : Not 100% tested. Max - Unit s ns SWITCHING WAVEFORMS tVCS tVCCmin Vcc/Vccq RESET CE VIH tRH Figure 3. Vcc Power-up Diagram 11.0 CAPACITANCE(TA = 25 C, VCC = 1.8V, f = 1.0MHz) Item Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V VIN=0V Min Max 10 10 10 Unit pF pF pF - 31 - K5N1229ACD-BQ12 datasheet Value 0V to VCC Rev. 1.0 MCP Memory 12.0 AC TEST CONDITION Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Address to Address Skew 3ns(max)@66Mhz, 2.5ns(max)@83Mhz, 1.5ns(max)@108Mhz, 1ns(max)@133Mhz VCC/2 CL = 30pF 3ns(max) VCC VCC/2 Input & Output Test Point VCC/2 Device Under Test 0V Input Pulse and Test Point (including CLK characterization) * CL = 30pF including scope and Jig capacitance Output Load 13.0 AC CHARACTERISTICS 13.1 Synchronous/Burst Read Parameter Initial Access Time Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK AVD Hold Time from CLK AVD High to OE Low Address Setup Time to CLK Address Hold Time from CLK Data Hold Time from Next Clock Cycle Output Enable to RDY valid CE Disable to High Z OE Disable to High Z CE Setup Time to CLK CE Enable to RDY active CLK to RDY Setup Time RDY Setup Time to CLK CLK period CLK High or Low Time CLK Fall or Rise Time Symbol tIAA tBA tAVDS tAVDH tAVDO tACS tACH tBDH tOER tCEZ tOEZ tCES tRDY tRDYA tRDYS tCLK tCLKH/L tCLKHCL 1C (66 MHz) Min 5 2 0 5 6 3 6 3 15.1 0.4x tCLK Max 95 11 11 9 9 11 11 0.6x tCLK 3 1D (83 MHz) Min 4 2 0 4 5 3 4.5 3 12.05 0.4x tCLK Max 95 9 9 9 9 9 9 0.6x tCLK 2.5 1E (108 MHz) Min 3.5 2 0 3.5 2 2 4 2 9.26 0.4x tCLK Max 95 7 7 9 9 7 7 0.6x tCLK 1.5 1F (133 MHz) Min 2.5 2 0 2.5 2 2 3.5 2 7.52 0.4x tCLK Max 95 6 6 9 9 6 6 0.6x tCLK 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit - 32 - K5N1229ACD-BQ12 datasheet 13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 7.5ns typ(133MHz). Rev. 1.0 MCP Memory SWITCHING WAVEFORMS tCES CE 1 2 tCEZ 3 4 5 11 12 13 CLK tAVDS tAVDS tAVDO tAVDH A16-A24 tACS Aa tACH A/DQ0: A/DQ15 AVD tBDH tBA Aa tIAA Hi-Z Da+n tOEZ Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6 OE tRDY RDY Hi-Z tOER tRDYS tRDYA Hi-Z Figure 4. Continuous Burst Mode Read (133 MHz) NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. 11 cycles for initial access shown. CR setting : A14=0, A13=1, A12=1, A11=1 tCES CE 11 1 2 3 4 9 10 9.25ns typ(108MHz). tCEZ CLK AVD tAVDS tAVDS tAVDO tAVDH tACS Aa tACH tBDH tBA A16-A24 A/DQ0: A/DQ15 Aa tIAA Hi-Z Da+n Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6 tOEZ OE tRDY RDY Hi-Z tOER Figure 5. Continuous Burst Mode Read (108 MHz) NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. tRDYS tRDYA Hi-Z - 33 - K5N1229ACD-BQ12 datasheet 13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 7.5ns typ(133MHz). Rev. 1.0 MCP Memory SWITCHING WAVEFORMS tCES CE 1 2 3 4 11 12 13 CLK tAVDS tAVDS tAVDO tAVDH A16-A24 tACS Aa tACH A/DQ0: A/DQ15 Aa tIAA AVD tBDH tBA D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 OE tRDY RDY Hi-Z tOER Figure 6. 8 word Linear Burst Mode with Wrap Around (133 MHz) NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. 13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 tCES CE 1 2 3 7.5ns typ(133MHz). 4 10 11 12 13 tRDYS tRDYA CLK tAVDS tAVDS tAVDO tAVDH A16-A24 tACS Aa tACH A/DQ0: A/DQ15 Aa AVD tBDH tBA tIAA D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 OE tRDY RDY Hi-Z tOER Figure 7. 8 word Linear Burst with RDY Set One Cycle Before Data (Wrap Around Mode, CR setting : A18=1) NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. tRDYS tRDYA - 34 - K5N1229ACD-BQ12 datasheet 13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 7.5ns typ(133MHz). Rev. 1.0 MCP Memory SWITCHING WAVEFORMS tCES CE 1 2 tCEZ 3 4 5 11 12 13 CLK AVD tAVDS tAVDS tAVDO tAVDH tACS Aa tACH tBDH A16-A24 tBA A/DQ0: A/DQ15 Aa tIAA Hi-Z D7 D8 D9 D10 D15 D6 D0 tOEZ OE tRDY RDY Hi-Z tOER Figure 8. 16 word Linear Burst Mode with Wrap Around (133Mhz) NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. tRDYS tRDYA Hi-Z - 35 - K5N1229ACD-BQ12 datasheet Parameter Symbol tCE tAA tAVDP tAAVDS tAAVDH tOE Read Toggle and Data Polling tOEH tOEZ Min 12 5 2 0 10 - Rev. 1.0 MCP Memory 13.2 Asynchronous Read All speed Max 100 100 15 9 Unit ns ns ns ns ns ns ns ns ns Access Time from CE Low Asynchronous Access Time AVD Low time Address Setup Time to rising Edge of AVD Address Hold Time from Rising Edge of AVD Output Enable to Output Valid Output Enable Hold Time Output Disable to High Z* NOTE: Not 100% tested. SWITCHING WAVEFORMS Asynchronous Mode Read (tCE) CE tOE OE tOEH WE A/DQ0: A/DQ15 tCE VA Valid RD tOEZ A16-A24 tAAVDS AVD Hi-Z VA tAAVDH tAVDP Hi-Z RDY Figure 9. Asynchronous Mode Read (tCE) NOTE : VA=Valid Read Address, RD=Read Data. Asynchronous mode may not support read following four sequential invalid read condition within 200ns. - 36 - K5N1229ACD-BQ12 datasheet tOE Rev. 1.0 MCP Memory Asynchronous Mode Read (tAA) Case 1 : Valid Address Transition occurs before AVD is driven to Low CE OE tOEH WE A/DQ0: A/DQ15 tOEZ VA tAA A16-A24 tAAVDS AVD tAVDP RDY Hi-Z Hi-Z VA tAAVDH Valid RD Case 2 : Valid Address Transition occurs after AVD is driven to Low CE tOE OE tOEH WE A/DQ0: A/DQ15 tOEZ VA tAA A16-A24 tAAVDS AVD Hi-Z tAVDP Hi-Z VA tAAVDH Valid RD RDY Figure 10. Asynchronous Mode Read (tAA) NOTE : 1) VA=Valid Read Address, RD=Read Data. 2) Asynchronous mode may not support read following four sequential invalid read condition within 200ns. - 37 - K5N1229ACD-BQ12 datasheet Symbol tReady tReady tRP tRH All Speed Options Min 200 200 Rev. 1.0 MCP Memory 13.3 Hardware Reset(RESET) Parameter RESET Pin Low(During Internal Routines) to Read Mode* RESET Pin Low(NOT During Internal Routines) to Read Mode* RESET Pulse Width Reset High Time Before Read* NOTE : Not 100% tested. Max 20 500 - Unit s ns ns ns SWITCHING WAVEFORMS CE, OE tRH RESET tRP tReady Reset Timings NOT during Internal Routines CE, OE tReady RESET tRP Reset Timings during Internal Routines Figure 11. Reset Timings - 38 - K5N1229ACD-BQ12 datasheet Symbol tWC tAS tAH tAVDP tDS tDH tGHWL tCS tCH tWEA tWP tWPH tSR/W tPGM tPGM_BP tPGM_BP 3) 3) Rev. 1.0 MCP Memory 13.4 Erase/Program Operation Parameter WE Cycle Time1) Address Setup Time Address Hold Time AVD Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE Setup Time CE Hold Time WE High to AVD low WE Pulse Width WE Pulse Width High Latency Between Read and Write Operations Word Programming Operation Single word Buffer Program 512-word Buffer Program 4) 2) 2) All speed options Min 75 5 2 12 30 0 0 0 0 30 30 45 0 500 1 Typ 80 250 716.8 80 0.7 358.4 0.6 7 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s sec ms ns s Accelerated Programming Operation tACCPGM tACCPGM_BP tACCPGM_BP tBERS tBLANK tVPP tVPS Accelerated Single word Buffer Program Accelerated 512-word Buffer Program Block Erase Operation (64KW block) Blank check Operation (64KW block) VPP Rise and Fall Time 4) VPP Setup Time (During Accelerated Programming) NOTE : 1) Not 100% tested. 2) Internal programming algorithm is optimized for Buffer Program, so Normal word programming or Single word Buffer Program use Buffer Program algorithm. 3) Internal programming algorithm for supporting Accelerated mode uses a method to double the number of words programmed simultaneously. 4) Typical 512-word Buffer Program time pays due regard to that Each program data pattern ("11", "10". "01", "00") has a same portion in 512-word Buffer. - 39 - K5N1229ACD-BQ12 datasheet Limits Min. 64 Kword 16 Kword 64 Kword 16 Kword Typ. 0.6 0.3 307.8 0.4 0.2 205.2 80 1.4 80 0.7 46.9 23.4 7 Max. 3.0 1.5 1539 3.0 1.5 1026 550 7 550 3.5 234.5 117 sec milli sec s / word sec Unit Rev. 1.0 MCP Memory 13.5 Erase/Program Performance Parameter Block Erase Time Chip Erase Time (3) Accelerated Block Erase Time Accelerated Chip Erase Time (3) Word Programming Time 512-word Buffer Programming Time Accelerated Word Programming Time Accelerated 512-word Buffer Programming Time Chip Buffer Programming Time Accelerated Buffer Chip Programming Time Blank check time NOTE : 1)25C, VCC = 1.8V, 100,000 cycles, typical pattern. 2) System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word. 3) Chip Erase time & Accel. Chip Erase time for boot block part Comments Includes 00h programming prior to erasure Excludes system level overhead - 40 - K5N1229ACD-BQ12 datasheet tAS Program Command Sequence (last two cycles) tWEA Rev. 1.0 MCP Memory SWITCHING WAVEFORMS Program Operations Read Status Data AVD tAVDP A16:A24 tAH PA VA VA A/DQ0: A/DQ15 555h A0h PA PD tDS tDH VA In Progress VA Complete CE OE tWP tCH WE tWPH tCS CLK VCC VIL tVCS tWC tPGM NOTE : 1) PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2) "In progress" and "complete" refer to status of program operation. 3) A16-A24 are don't care during command sequence unlock cycles. 4) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. Figure 12. Program Operation Timing - 41 - K5N1229ACD-BQ12 datasheet Word Count Rev. 1.0 MCP Memory SWITCHING WAVEFORMS Buffer Program Operations Buffer Program Command Sequence tAS AVD tAH A16:A24 tAVDP BA BA PA_0 PA_1 PA_N BA Program Address/Data pairs (WC+1) "Buffer to Flash" A/DQ0: A/DQ15 555h A0h tDS 2AAh 55h BA 25h BA WC PA_0 PD_0 PA_1 PD_1 PA_N PD_N BA 29h CE OE tWP WE tCS CLK VCC VIL tWPH tWC tPGM_BP tVCS NOTE : 1) BA = Block Address, WC = Word Count, PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2) Sequential PA_1, PA_2, ... , PA_N must have same address bits A24(max.) ~ A9 as PA_0 entered firstly 3) The number of Program/Data pairs entered must be same as WC+1 because WC = N. 4) "In progress" and "complete" refer to status of program operation. 5) A16-A24 are don't care during command sequence unlock cycles. 6) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. Figure 13. Buffer Program Operation Timing - 42 - K5N1229ACD-BQ12 datasheet tAS Erase Command Sequence (last two cycles) tWEA Rev. 1.0 MCP Memory SWITCHING WAVEFORMS Erase Operation Read Status Data AVD tAVDP A16:A24 tAH BA 555h for chip erase 2AAh 55h BA 10h for chip erase 30h tDS CE tDH VA VA A/DQ0: A/DQ15 VA In Progress VA Complete OE tWP tCH WE tWPH tCS CLK VCC VIL tVCS tWC tBERS NOTE : 1) BA is the block address for Block Erase. 2) Address bits A16-A24 are don't cares during unlock cycles in the command sequence. 3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. Figure 14. Chlp/Block Erase Operations - 43 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program) CE AVD WE A16:A24 PA A/DQ0: A/DQ15 Don't Care A0h PA PD Don't Care OE tVPS VID VPP VIL or VIH tVPP Unlock Bypass Block Erase Operations CE AVD WE A16:A24 BA 555h for chip erase Don't Care 80h BA 10h for chip erase 30h Don't Care A/DQ0: A/DQ15 OE tVPS VID VPP VIL or VIH tVPP NOTE : 1) VPP can be left high for subsequent programming pulses. 2) Use setup and hold times from conventional program operations. 3) Conventional Program/Erase commands as well as Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp. Figure 15. Unlock Bypass Operation Timings - 44 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory SWITCHING WAVEFORMS Data Polling Operations tCES CE CLK tAVDS AVD tAVDH A16-A24 tACS VA tACH A/DQ0: A/DQ15 VA tIAA OE Hi-Z tRDYS Status Data VA VA Status Data RDY NOTE : 1) VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data. Figure 16. Data Polling Timings (During Internal Routine) Toggle Bit Operations tCES CE CLK tAVDS AVD tAVDH A16-A24 tACS VA tACH A/DQ0: A/DQ15 VA tIAA OE Hi-Z tRDYS Status Data VA VA Status Data RDY NOTE : 1) VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling. Figure 17. Toggle Bit Timings(During Internal Routine) - 45 - K5N1229ACD-BQ12 datasheet Last Cycle in Program or Block Erase Command Sequence Read status in same bank and/or array data from other bank Rev. 1.0 MCP Memory SWITCHING WAVEFORMS Read While Write Operations Begin another Program or Erase Command Sequences tWC CE tRC tRC tWC OE tOE tOEH WE tWPH A/DQ0: A/DQ15 PA/BA tWP tDS PD/30h tAA tDH RA tSR/W A16-A24 RD tGHWL tOEH RA RD 555h AAh PA/BA tAS RA RA AVD tAH Figure 18. Read While Write Operation NOTE : Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" and checking the status of the program or erase operation in the "busy" bank. - 46 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 14.0 Crossing of First Word Boundary in Burst Read Mode The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no additional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of additional clock cycle for the first word boundary can vary from zero to thirteen cycles, and the exact number of additional clock cycle depends on the starting address of burst read and programmable wait state settings. For example, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A14~A11) is "0011" (which means data is valid on the 7th active CLK edge after AVD transition to Vih), six additional clock cycle is needed. Similarly, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A14~A11) is "0010" (which means data is valid on the 6th active CLK edge after AVD transition to Vih), five additional clock cycle is needed. Below table shows the starting address vs. additional clock cycles for first word boundary. Starting Address vs. Additional Clock Cycles for first word boundary Srarting Address Group for Burst Read 16N 16N+1 16N+2 16N+3 16N+4 16N+5 16N+6 16N+7 16N+8 16N+9 16N+10 16N+11 16N+12 16N+13 16N+14 16N+15 The Residue of (Address/16) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LSB Bits of Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Additional Clock Cycles for First Word Boundary 1) A14~A11 "0000" Valid data : 4th CLK 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle A14~A11 "0001" Valid data : 5th CLK 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle A14~A11 "0010" Valid data : 6th CLK 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... A14~A11 "1010" Valid data : 14th CLK 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle 13 cycle NOTE : 1) Address bit A14~A11 means the programmable wait state on burst mode configuration register. Refer to Table 10. - 47 - K5N1229ACD-BQ12 datasheet CR setting : A14=1, A13=0, A12=1, A11=0 14th rising edge CLK Rev. 1.0 MCP Memory Case 1 : Start from "16N" address group A16-A24 A/DQ0: A/DQ15 CLK Aa Aa 0B 0C 0D 0E 0F 10 11 12 00 0B 0C 0D 0E 0F 10 11 12 13 AVD No Additional Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY NOTE : 1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc. 2) Address 000000H is also a boundary crossing. 3) No additional clock cycles are needed except for 1st boundary crossing. Figure 19. Crossing of first word boundary in burst read mode. Case 2 : Start from "16N+3" address group CR setting : A14=1, A13=0, A12=1, A11=0 14th rising edge CLK A16-A24 A/DQ0: A/DQ15 CLK Aa Aa 0D 0E 0F 10 11 12 13 00 0D 0E 0F 10 11 12 13 14 AVD Additional 1 Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY NOTE : 1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc. 2) Address 000000H is also a boundary crossing. 3) No additional clock cycles are needed except for 1st boundary crossing. Figure 20. Crossing of first word boundary in burst read mode. - 48 - K5N1229ACD-BQ12 datasheet CR setting : A14=1, A13=0, A12=1, A11=0 14th rising edge CLK Rev. 1.0 MCP Memory Case3 : Start from "16N+4" address group A16-A24 A/DQ0: A/DQ15 CLK Aa Aa 0E 0F 10 11 12 13 00 0E 0F 10 11 12 13 14 AVD Additional 2 Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY Case 4 : Start from "16N+15" address group CR setting : A14=1, A13=0, A12=1, A11=0 14th rising edge CLK A16-A24 A/DQ0: A/DQ15 CLK Aa Aa 3F 10 11 00 3F 10 11 12 AVD Additional 13 Cycle for First Word Boundary CE OE tOER RDY NOTE : 1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc. 2) Address 000000H is also a boundary crossing. 3) No additional clock cycles are needed except for 1st boundary crossing. Figure 21. Crossing of first word boundary in burst read mode. - 49 - K5N1229ACD-BQ12 datasheet Block Size 16 kwords 16 kwords 16 kwords 16 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1FFC000h-1FFFFFFh 1FF8000h-1FFBFFFh 1FF4000h-1FF7FFFh 1FF0000h-1FF3FFFh 1FE0000h-1FEFFFFh 1FD0000h-1FDFFFFh 1FC0000h-1FCFFFFh 1FB0000h-1FBFFFFh 1FA0000h-1FAFFFFh 1F90000h-1F9FFFFh 1F80000h-1F8FFFFh 1F70000h-1F7FFFFh 1F60000h-1F6FFFFh 1F50000h-1F5FFFFh 1F40000h-1F4FFFFh 1F30000h-1F3FFFFh 1F20000h-1F2FFFFh 1F10000h-1F1FFFFh 1F00000h-1F0FFFFh 1EF0000h-1EFFFFFh 1EE0000h-1EEFFFFh 1ED0000h-1EDFFFFh 1EC0000h-1ECFFFFh 1EB0000h-1EBFFFFh 1EA0000h-1EAFFFFh 1E90000h-1E9FFFFh 1E80000h-1E8FFFFh 1E70000h-1E7FFFFh 1E60000h-1E6FFFFh 1E50000h-1E5FFFFh 1E40000h-1E4FFFFh 1E30000h-1E3FFFFh 1E20000h-1E2FFFFh 1E10000h-1E1FFFFh 1E00000h-1E0FFFFh 1DF0000h-1DFFFFFh 1DE0000h-1DEFFFFh 1DD0000h-1DDFFFFh 1DC0000h-1DCFFFFh 1DB0000h-1DBFFFFh 1DA0000h-1DAFFFFh 1D90000h-1D9FFFFh 1D80000h-1D8FFFFh 1D70000h-1D7FFFFh 1D60000h-1D6FFFFh [Table 16] Top Boot Block Address Table Bank Block BA514 BA513 BA512 BA511 BA510 BA509 BA508 BA507 BA506 BA505 BA504 BA503 BA502 BA501 BA500 BA499 BA498 Bank 0 BA497 BA496 BA495 BA494 BA493 BA492 BA491 BA490 BA489 BA488 BA487 BA486 BA485 BA484 BA483 BA482 BA481 BA480 BA479 BA478 BA477 BA476 Bank 1 BA475 BA474 BA473 BA472 BA471 BA470 - 50 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1D50000h-1D5FFFFh 1D40000h-1D4FFFFh 1D30000h-1D3FFFFh 1D20000h-1D2FFFFh 1D10000h-1D1FFFFh 1D00000h-1D0FFFFh 1CF0000h-1CFFFFFh 1CE0000h-1CEFFFFh 1CD0000h-1CDFFFFh 1CC0000h-1CCFFFFh 1CB0000h-1CBFFFFh 1CA0000h-1CAFFFFh 1C90000h-1C9FFFFh 1C80000h-1C8FFFFh 1C70000h-1C7FFFFh 1C60000h-1C6FFFFh 1C50000h-1C5FFFFh 1C40000h-1C4FFFFh 1C30000h-1C3FFFFh 1C20000h-1C2FFFFh 1C10000h-1C1FFFFh 1C00000h-1C0FFFFh 1BF0000h-1BFFFFFh 1BE0000h-1BEFFFFh 1BD0000h-1BDFFFFh 1BC0000h-1BCFFFFh 1BB0000h-1BBFFFFh 1BA0000h-1BAFFFFh 1B90000h-1B9FFFFh 1B80000h-1B8FFFFh 1B70000h-1B7FFFFh 1B60000h-1B6FFFFh 1B50000h-1B5FFFFh 1B40000h-1B4FFFFh 1B30000h-1B3FFFFh 1B20000h-1B2FFFFh 1B10000h-1B1FFFFh 1B00000h-1B0FFFFh 1AF0000h-1AFFFFFh 1AE0000h-1AEFFFFh 1AD0000h-1ADFFFFh 1AC0000h-1ACFFFFh 1AB0000h-1ABFFFFh 1AA0000h-1AAFFFFh 1A90000h-1A9FFFFh Bank Block BA469 BA468 BA467 BA466 BA465 BA464 BA463 BA462 BA461 BA460 Bank 1 BA459 BA458 BA457 BA456 BA455 BA454 BA453 BA452 BA451 BA450 BA449 BA448 BA447 BA446 BA445 BA444 BA443 BA442 BA441 BA440 BA439 BA438 BA437 Bank 2 BA436 BA435 BA434 BA433 BA432 BA431 BA430 BA429 BA428 BA427 BA426 BA425 - 51 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1A80000h-1A8FFFFh 1A70000h-1A7FFFFh 1A60000h-1A6FFFFh 1A50000h-1A5FFFFh 1A40000h-1A4FFFFh 1A30000h-1A3FFFFh 1A20000h-1A2FFFFh 1A10000h-1A1FFFFh 1A00000h-1A0FFFFh 19F0000h-19FFFFFh 19E0000h-19EFFFFh 19D0000h-19DFFFFh 19C0000h-19CFFFFh 19B0000h-19BFFFFh 19A0000h-19AFFFFh 1990000h-199FFFFh 1980000h-198FFFFh 1970000h-197FFFFh 1960000h-196FFFFh 1950000h-195FFFFh 1940000h-194FFFFh 1930000h-193FFFFh 1920000h-192FFFFh 1910000h-191FFFFh 1900000h-190FFFFh 18F0000h-18FFFFFh 18E0000h-18EFFFFh 18D0000h-18DFFFFh 18C0000h-18CFFFFh 18B0000h-18BFFFFh 18A0000h-18AFFFFh 1890000h-189FFFFh 1880000h-188FFFFh 1870000h-187FFFFh 1860000h-186FFFFh 1850000h-185FFFFh 1840000h-184FFFFh 1830000h-183FFFFh 1820000h-182FFFFh 1810000h-181FFFFh 1800000h-180FFFFh 17F0000h-17FFFFFh 17E0000h-17EFFFFh 17D0000h-17DFFFFh 17C0000h-17CFFFFh Bank Block BA424 BA423 BA422 BA421 Bank 2 BA420 BA419 BA418 BA417 BA416 BA415 BA414 BA413 BA412 BA411 BA410 BA409 BA408 BA407 BA406 BA405 BA404 BA403 BA402 BA401 Bank 3 BA400 BA399 BA398 BA397 BA396 BA395 BA394 BA393 BA392 BA391 BA390 BA389 BA388 BA387 BA386 BA385 BA384 BA383 Bank 4 BA382 BA381 BA380 - 52 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 17B0000h-17BFFFFh 17A0000h-17AFFFFh 1790000h-179FFFFh 1780000h-178FFFFh 1770000h-177FFFFh 1760000h-176FFFFh 1750000h-175FFFFh 1740000h-174FFFFh 1730000h-173FFFFh 1720000h-172FFFFh 1710000h-171FFFFh 1700000h-170FFFFh 16F0000h-16FFFFFh 16E0000h-16EFFFFh 16D0000h-16DFFFFh 16C0000h-16CFFFFh 16B0000h-16BFFFFh 16A0000h-16AFFFFh 1690000h-169FFFFh 1680000h-168FFFFh 1670000h-167FFFFh 1660000h-166FFFFh 1650000h-165FFFFh 1640000h-164FFFFh 1630000h-163FFFFh 1620000h-162FFFFh 1610000h-161FFFFh 1600000h-160FFFFh 15F0000h-15FFFFFh 15E0000h-15EFFFFh 15D0000h-15DFFFFh 15C0000h-15CFFFFh 15B0000h-15BFFFFh 15A0000h-15AFFFFh 1590000h-159FFFFh 1580000h-158FFFFh 1570000h-157FFFFh 1560000h-156FFFFh 1550000h-155FFFFh 1540000h-154FFFFh 1530000h-153FFFFh 1520000h-152FFFFh 1510000h-151FFFFh 1500000h-150FFFFh Bank Block BA379 BA378 BA377 BA376 BA375 BA374 BA373 BA372 BA371 BA370 BA369 BA368 BA367 Bank 4 BA366 BA365 BA364 BA363 BA362 BA361 BA360 BA359 BA358 BA357 BA356 BA355 BA354 BA353 BA352 BA351 BA350 BA349 BA348 BA347 BA346 BA345 Bank5 BA344 BA343 BA342 BA341 BA340 BA339 BA338 BA337 BA336 - 53 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 14F0000h-14FFFFFh 14E0000h-14EFFFFh 14D0000h-14DFFFFh 14C0000h-14CFFFFh 14B0000h-14BFFFFh 14A0000h-14AFFFFh 1490000h-149FFFFh 1480000h-148FFFFh 1470000h-147FFFFh 1460000h-146FFFFh 1450000h-145FFFFh 1440000h-144FFFFh 1430000h-143FFFFh 1420000h-142FFFFh 1410000h-141FFFFh 1400000h-140FFFFh 13F0000h-13FFFFFh 13E0000h-13EFFFFh 13D0000h-13DFFFFh 13C0000h-13CFFFFh 13B0000h-13BFFFFh 13A0000h-13AFFFFh 1390000h-139FFFFh 1380000h-138FFFFh 1370000h-137FFFFh 1360000h-136FFFFh 1350000h-135FFFFh 1340000h-134FFFFh 1330000h-133FFFFh 1320000h-132FFFFh 1310000h-131FFFFh 1300000h-130FFFFh 12F0000h-12FFFFFh 12E0000h-12EFFFFh 12D0000h-12DFFFFh 12C0000h-12CFFFFh 12B0000h-12BFFFFh 12A0000h-12AFFFFh 1290000h-129FFFFh 1280000h-128FFFFh 1270000h-127FFFFh 1260000h-126FFFFh 1250000h-125FFFFh 1240000h-124FFFFh 1230000h-123FFFFh Bank Block BA335 BA334 BA333 BA332 BA331 BA330 BA329 Bank 5 BA328 BA327 BA326 BA325 BA324 BA323 BA322 BA321 BA320 BA319 BA318 BA317 BA316 BA315 BA314 BA313 BA312 BA311 BA310 BA309 BA308 BA307 BA306 Bank 6 BA305 BA304 BA303 BA302 BA301 BA300 BA299 BA298 BA297 BA296 BA295 BA294 BA293 BA292 BA291 - 54 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1220000h-122FFFFh 1210000h-121FFFFh 1200000h-120FFFFh 11F0000h-11FFFFFh 11E0000h-11EFFFFh 11D0000h-11DFFFFh 11C0000h-11CFFFFh 11B0000h-11BFFFFh 11A0000h-11AFFFFh 1190000h-119FFFFh 1180000h-118FFFFh 1170000h-117FFFFh 1160000h-116FFFFh 1150000h-115FFFFh 1140000h-114FFFFh 1130000h-113FFFFh 1120000h-112FFFFh 1110000h-111FFFFh 1100000h-110FFFFh 10F0000h-10FFFFFh 10E0000h-10EFFFFh 10D0000h-10DFFFFh 10C0000h-10CFFFFh 10B0000h-10BFFFFh 10A0000h-10AFFFFh 1090000h-109FFFFh 1080000h-108FFFFh 1070000h-107FFFFh 1060000h-106FFFFh 1050000h-105FFFFh 1040000h-104FFFFh 1030000h-103FFFFh Bank Block BA290 Bank 6 BA289 BA288 BA287 BA286 BA285 BA284 BA283 BA282 BA281 BA280 BA279 BA278 BA277 BA276 BA275 BA274 Bank 7 BA273 BA272 BA271 BA270 BA269 BA268 BA267 BA266 BA265 BA264 BA263 BA262 BA261 BA260 BA259 - 55 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1020000h-102FFFFh 1010000h-101FFFFh 1000000h-100FFFFh 0FF0000h-0FFFFFFh 0FE0000h-0FEFFFFh 0FD0000h-0FDFFFFh 0FC0000h-0FCFFFFh 0FB0000h-0FBFFFFh 0FA0000h-0FAFFFFh 0F90000h-0F9FFFFh 0F80000h-0F8FFFFh 0F70000h-0F7FFFFh 0F60000h-0F6FFFFh 0F50000h-0F5FFFFh 0F40000h-0F4FFFFh 0F30000h-0F3FFFFh 0F20000h-0F2FFFFh 0F10000h-0F1FFFFh 0F00000h-0F0FFFFh 0EF0000h-0EFFFFFh 0EE0000h-0EEFFFFh 0ED0000h-0EDFFFFh 0EC0000h-0ECFFFFh 0EB0000h-0EBFFFFh 0EA0000h-0EAFFFFh 0E90000h-0E9FFFFh 0E80000h-0E8FFFFh 0E70000h-0E7FFFFh 0E60000h-0E6FFFFh 0E50000h-0E5FFFFh 0E40000h-0E4FFFFh 0E30000h-0E3FFFFh 0E20000h-0E2FFFFh 0E10000h-0E1FFFFh 0E00000h-0E0FFFFh 0DF0000h-0DFFFFFh 0DE0000h-0DEFFFFh 0DD0000h-0DDFFFFh 0DC0000h-0DCFFFFh 0DB0000h-0DBFFFFh 0DA0000h-0DAFFFFh 0D90000h-0D9FFFFh 0D80000h-0D8FFFFh 0D70000h-0D7FFFFh 0D60000h-0D6FFFFh Bank Block BA258 Bank 7 BA257 BA256 BA255 BA254 BA253 BA252 BA251 BA250 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 Bank 8 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 BA220 Bank 9 BA219 BA218 BA217 BA216 BA215 BA214 - 56 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0D50000h-0D5FFFFh 0D40000h-0D4FFFFh 0D30000h-0D3FFFFh 0D20000h-0D2FFFFh 0D10000h-0D1FFFFh 0D00000h-0D0FFFFh 0CF0000h-0CFFFFFh 0CE0000h-0CEFFFFh 0CD0000h-0CDFFFFh 0CC0000h-0CCFFFFh 0CB0000h-0CBFFFFh 0CA0000h-0CAFFFFh 0C90000h-0C9FFFFh 0C80000h-0C8FFFFh 0C70000h-0C7FFFFh 0C60000h-0C6FFFFh 0C50000h-0C5FFFFh 0C40000h-0C4FFFFh 0C30000h-0C3FFFFh 0C20000h-0C2FFFFh 0C10000h-0C1FFFFh 0C00000h-0C0FFFFh 0BF0000h-0BFFFFFh 0BE0000h-0BEFFFFh 0BD0000h-0BDFFFFh 0BC0000h-0BCFFFFh 0BB0000h-0BBFFFFh 0BA0000h-0BAFFFFh 0B90000h-0B9FFFFh 0B80000h-0B8FFFFh 0B70000h-0B7FFFFh 0B60000h-0B6FFFFh 0B50000h-0B5FFFFh 0B40000h-0B4FFFFh 0B30000h-0B3FFFFh 0B20000h-0B2FFFFh 0B10000h-0B1FFFFh 0B00000h-0B0FFFFh 0AF0000h-0AFFFFFh 0AE0000h-0AEFFFFh 0AD0000h-0ADFFFFh 0AC0000h-0ACFFFFh 0AB0000h-0ABFFFFh 0AA0000h-0AAFFFFh 0A90000h-0A9FFFFh Bank Block BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 Bank 9 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 Bank 10 BA180 BA179 BA178 BA177 BA176 BA175 BA174 BA173 BA172 BA171 BA170 BA169 - 57 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0A80000h-0A8FFFFh 0A70000h-0A7FFFFh 0A60000h-0A6FFFFh 0A50000h-0A5FFFFh 0A40000h-0A4FFFFh 0A30000h-0A3FFFFh 0A20000h-0A2FFFFh 0A10000h-0A1FFFFh 0A00000h-0A0FFFFh 09F0000h-09FFFFFh 09E0000h-09EFFFFh 09D0000h-09DFFFFh 09C0000h-09CFFFFh 09B0000h-09BFFFFh 09A0000h-09AFFFFh 0990000h-099FFFFh 0980000h-098FFFFh 0970000h-097FFFFh 0960000h-096FFFFh 0950000h-095FFFFh 0940000h-094FFFFh 0930000h-093FFFFh 0920000h-092FFFFh 0910000h-091FFFFh 0900000h-090FFFFh 08F0000h-08FFFFFh 08E0000h-08EFFFFh 08D0000h-08DFFFFh 08C0000h-08CFFFFh 08B0000h-08BFFFFh 08A0000h-08AFFFFh 0890000h-089FFFFh 0880000h-088FFFFh 0870000h-087FFFFh 0860000h-086FFFFh 0850000h-085FFFFh 0840000h-084FFFFh 0830000h-083FFFFh 0820000h-082FFFFh 0810000h-081FFFFh 0800000h-080FFFFh 07F0000h-07FFFFFh 07E0000h-07EFFFFh 07D0000h-07DFFFFh 07C0000h-07CFFFFh Bank Block BA168 BA167 BA166 BA165 Bank 10 BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 Bank 11 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 Bank 12 BA126 BA125 BA124 - 58 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 07B0000h-07BFFFFh 07A0000h-07AFFFFh 0790000h-079FFFFh 0780000h-078FFFFh 0770000h-077FFFFh 0760000h-076FFFFh 0750000h-075FFFFh 0740000h-074FFFFh 0730000h-073FFFFh 0720000h-072FFFFh 0710000h-071FFFFh 0700000h-070FFFFh 06F0000h-06FFFFFh 06E0000h-06EFFFFh 06D0000h-06DFFFFh 06C0000h-06CFFFFh 06B0000h-06BFFFFh 06A0000h-06AFFFFh 0690000h-069FFFFh 0680000h-068FFFFh 0670000h-067FFFFh 0660000h-066FFFFh 0650000h-065FFFFh 0640000h-064FFFFh 0630000h-063FFFFh 0620000h-062FFFFh 0610000h-061FFFFh 0600000h-060FFFFh 05F0000h-05FFFFFh 05E0000h-05EFFFFh 05D0000h-05DFFFFh 05C0000h-05CFFFFh 05B0000h-05BFFFFh 05A0000h-05AFFFFh 0590000h-059FFFFh 0580000h-058FFFFh 0570000h-057FFFFh 0560000h-056FFFFh 0550000h-055FFFFh 0540000h-054FFFFh 0530000h-053FFFFh 0520000h-052FFFFh 0510000h-051FFFFh 0500000h-050FFFFh Bank Block BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 Bank 12 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 Bank13 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80 - 59 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 04F0000h-04FFFFFh 04E0000h-04EFFFFh 04D0000h-04DFFFFh 04C0000h-04CFFFFh 04B0000h-04BFFFFh 04A0000h-04AFFFFh 0490000h-049FFFFh 0480000h-048FFFFh 0470000h-047FFFFh 0460000h-046FFFFh 0450000h-045FFFFh 0440000h-044FFFFh 0430000h-043FFFFh 0420000h-042FFFFh 0410000h-041FFFFh 0400000h-040FFFFh 03F0000h-03FFFFFh 03E0000h-03EFFFFh 03D0000h-03DFFFFh 03C0000h-03CFFFFh 03B0000h-03BFFFFh 03A0000h-03AFFFFh 0390000h-039FFFFh 0380000h-038FFFFh 0370000h-037FFFFh 0360000h-036FFFFh 0350000h-035FFFFh 0340000h-034FFFFh 0330000h-033FFFFh 0320000h-032FFFFh 0310000h-031FFFFh 0300000h-030FFFFh 02F0000h-02FFFFFh 02E0000h-02EFFFFh 02D0000h-02DFFFFh 02C0000h-02CFFFFh 02B0000h-02BFFFFh 02A0000h-02AFFFFh 0290000h-029FFFFh 0280000h-028FFFFh 0270000h-027FFFFh 0260000h-026FFFFh 0250000h-025FFFFh 0240000h-024FFFFh 0230000h-023FFFFh Bank Block BA79 BA78 BA77 BA76 BA75 BA74 BA73 Bank 13 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 Bank 14 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 - 60 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0220000h-022FFFFh 0210000h-021FFFFh 0200000h-020FFFFh 01F0000h-01FFFFFh 01E0000h-01EFFFFh 01D0000h-01DFFFFh 01C0000h-01CFFFFh 01B0000h-01BFFFFh 01A0000h-01AFFFFh 0190000h-019FFFFh 0180000h-018FFFFh 0170000h-017FFFFh 0160000h-016FFFFh 0150000h-015FFFFh 0140000h-014FFFFh 0130000h-013FFFFh 0120000h-012FFFFh 0110000h-011FFFFh 0100000h-010FFFFh 00F0000h-00FFFFFh 00E0000h-00EFFFFh 00D0000h-00DFFFFh 00C0000h-00CFFFFh 00B0000h-00BFFFFh 00A0000h-00AFFFFh 0090000h-009FFFFh 0080000h-008FFFFh 0070000h-007FFFFh 0060000h-006FFFFh 0050000h-005FFFFh 0040000h-004FFFFh 0030000h-003FFFFh 0020000h-002FFFFh 0010000h-001FFFFh 0000000h-000FFFFh Bank Block BA34 Bank 14 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 Bank 15 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 [Table 17] Top Boot OTP Block Addresses OTP Block Address A24 ~ A8 1FFFFh Block Size 512 words (x16) Address Range* 1FFFE00h-1FFFFFFh After entering OTP Block, any issued addresses should be in the range of OTP block address. - 61 - K5N1229ACD-BQ12 datasheet Block Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1FF0000h-1FFFFFFh 1FE0000h-1FEFFFFh 1FD0000h-1FDFFFFh 1FC0000h-1FCFFFFh 1FB0000h-1FBFFFFh 1FA0000h-1FAFFFFh 1F90000h-1F9FFFFh 1F80000h-1F8FFFFh 1F70000h-1F7FFFFh 1F60000h-1F6FFFFh 1F50000h-1F5FFFFh 1F40000h-1F4FFFFh 1F30000h-1F3FFFFh 1F20000h-1F2FFFFh 1F10000h-1F1FFFFh 1F00000h-1F0FFFFh 1EF0000h-1EFFFFFh 1EE0000h-1EEFFFFh 1ED0000h-1EDFFFFh 1EC0000h-1ECFFFFh 1EB0000h-1EBFFFFh 1EA0000h-1EAFFFFh 1E90000h-1E9FFFFh 1E80000h-1E8FFFFh 1E70000h-1E7FFFFh 1E60000h-1E6FFFFh 1E50000h-1E5FFFFh 1E40000h-1E4FFFFh 1E30000h-1E3FFFFh 1E20000h-1E2FFFFh 1E10000h-1E1FFFFh 1E00000h-1E0FFFFh 1DF0000h-1DFFFFFh 1DE0000h-1DEFFFFh 1DD0000h-1DDFFFFh 1DC0000h-1DCFFFFh 1DB0000h-1DBFFFFh 1DA0000h-1DAFFFFh 1D90000h-1D9FFFFh 1D80000h-1D8FFFFh 1D70000h-1D7FFFFh 1D60000h-1D6FFFFh 1D50000h-1D5FFFFh 1D40000h-1D4FFFFh 1D30000h-1D3FFFFh [Table 18] Bottom Boot Block Address Table Bank Block BA514 BA513 BA512 BA511 BA510 BA509 BA508 BA507 BA506 BA505 BA504 BA503 BA502 BA501 BA500 Bank 15 BA499 BA498 BA497 BA496 BA495 BA494 BA493 BA492 BA491 BA490 BA489 BA488 BA487 BA486 BA485 BA484 BA483 BA482 BA481 BA480 BA479 BA478 BA477 Bank 14 BA476 BA475 BA474 BA473 BA472 BA471 BA470 - 62 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1D20000h-1D2FFFFh 1D10000h-1D1FFFFh 1D00000h-1D0FFFFh 1CF0000h-1CFFFFFh 1CE0000h-1CEFFFFh 1CD0000h-1CDFFFFh 1CC0000h-1CCFFFFh 1CB0000h-1CBFFFFh 1CA0000h-1CAFFFFh 1C90000h-1C9FFFFh 1C80000h-1C8FFFFh 1C70000h-1C7FFFFh 1C60000h-1C6FFFFh 1C50000h-1C5FFFFh 1C40000h-1C4FFFFh 1C30000h-1C3FFFFh 1C20000h-1C2FFFFh 1C10000h-1C1FFFFh 1C00000h-1C0FFFFh 1BF0000h-1BFFFFFh 1BE0000h-1BEFFFFh 1BD0000h-1BDFFFFh 1BC0000h-1BCFFFFh 1BB0000h-1BBFFFFh 1BA0000h-1BAFFFFh 1B90000h-1B9FFFFh 1B80000h-1B8FFFFh 1B70000h-1B7FFFFh 1B60000h-1B6FFFFh 1B50000h-1B5FFFFh 1B40000h-1B4FFFFh 1B30000h-1B3FFFFh 1B20000h-1B2FFFFh 1B10000h-1B1FFFFh 1B00000h-1B0FFFFh 1AF0000h-1AFFFFFh 1AE0000h-1AEFFFFh 1AD0000h-1ADFFFFh 1AC0000h-1ACFFFFh 1AB0000h-1ABFFFFh 1AA0000h-1AAFFFFh 1A90000h-1A9FFFFh 1A80000h-1A8FFFFh 1A70000h-1A7FFFFh 1A60000h-1A6FFFFh Bank Block BA469 BA468 BA467 BA466 BA465 BA464 BA463 BA462 BA461 Bank 14 BA460 BA459 BA458 BA457 BA456 BA455 BA454 BA453 BA452 BA451 BA450 BA449 BA448 BA447 BA446 BA445 BA444 BA443 BA442 BA441 BA440 BA439 Bank 13 BA438 BA437 BA436 BA435 BA434 BA433 BA432 BA431 BA430 BA429 BA428 BA427 BA426 BA425 - 63 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1A50000h-1A5FFFFh 1A40000h-1A4FFFFh 1A30000h-1A3FFFFh 1A20000h-1A2FFFFh 1A10000h-1A1FFFFh 1A00000h-1A0FFFFh 19F0000h-19FFFFFh 19E0000h-19EFFFFh 19D0000h-19DFFFFh 19C0000h-19CFFFFh 19B0000h-19BFFFFh 19A0000h-19AFFFFh 1990000h-199FFFFh 1980000h-198FFFFh 1970000h-197FFFFh 1960000h-196FFFFh 1950000h-195FFFFh 1940000h-194FFFFh 1930000h-193FFFFh 1920000h-192FFFFh 1910000h-191FFFFh 1900000h-190FFFFh 18F0000h-18FFFFFh 18E0000h-18EFFFFh 18D0000h-18DFFFFh 18C0000h-18CFFFFh 18B0000h-18BFFFFh 18A0000h-18AFFFFh 1890000h-189FFFFh 1880000h-188FFFFh 1870000h-187FFFFh 1860000h-186FFFFh 1850000h-185FFFFh 1840000h-184FFFFh 1830000h-183FFFFh 1820000h-182FFFFh 1810000h-181FFFFh 1800000h-180FFFFh 17F0000h-17FFFFFh 17E0000h-17EFFFFh 17D0000h-17DFFFFh 17C0000h-17CFFFFh 17B0000h-17BFFFFh 17A0000h-17AFFFFh 1790000h-179FFFFh Bank Block BA424 BA423 Bank 13 BA422 BA421 BA420 BA419 BA418 BA417 BA416 BA415 BA414 BA413 BA412 BA411 BA410 BA409 BA408 BA407 BA406 BA405 BA404 Bank 12 BA403 BA402 BA401 BA400 BA399 BA398 BA397 BA396 BA395 BA394 BA393 BA392 BA391 BA390 BA389 BA388 BA387 BA386 BA385 BA384 Bank 11 BA383 BA382 BA381 BA380 - 64 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1780000h-178FFFFh 1770000h-177FFFFh 1760000h-176FFFFh 1750000h-175FFFFh 1740000h-174FFFFh 1730000h-173FFFFh 1720000h-172FFFFh 1710000h-171FFFFh 1700000h-170FFFFh 16F0000h-16FFFFFh 16E0000h-16EFFFFh 16D0000h-16DFFFFh 16C0000h-16CFFFFh 16B0000h-16BFFFFh 16A0000h-16AFFFFh 1690000h-169FFFFh 1680000h-168FFFFh 1670000h-167FFFFh 1660000h-166FFFFh 1650000h-165FFFFh 1640000h-164FFFFh 1630000h-163FFFFh 1620000h-162FFFFh 1610000h-161FFFFh 1600000h-160FFFFh 15F0000h-15FFFFFh 15E0000h-15EFFFFh 15D0000h-15DFFFFh 15C0000h-15CFFFFh 15B0000h-15BFFFFh 15A0000h-15AFFFFh 1590000h-159FFFFh 1580000h-158FFFFh 1570000h-157FFFFh 1560000h-156FFFFh 1550000h-155FFFFh 1540000h-154FFFFh 1530000h-153FFFFh 1520000h-152FFFFh 1510000h-151FFFFh 1500000h-150FFFFh 14F0000h-14FFFFFh 14E0000h-14EFFFFh 14D0000h-14DFFFFh Bank Block BA379 BA378 BA377 BA376 BA375 BA374 BA373 BA372 BA371 BA370 BA369 BA368 Bank 11 BA367 BA366 BA365 BA364 BA363 BA362 BA361 BA360 BA359 BA358 BA357 BA356 BA355 BA354 BA353 BA352 BA351 BA350 BA349 BA348 BA347 BA346 Bank 10 BA345 BA344 BA343 BA342 BA341 BA340 BA339 BA338 BA337 BA336 - 65 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 14C0000h-14CFFFFh 14B0000h-14BFFFFh 14A0000h-14AFFFFh 1490000h-149FFFFh 1480000h-148FFFFh 1470000h-147FFFFh 1460000h-146FFFFh 1450000h-145FFFFh 1440000h-144FFFFh 1430000h-143FFFFh 1420000h-142FFFFh 1410000h-141FFFFh 1400000h-140FFFFh 13F0000h-13FFFFFh 13E0000h-13EFFFFh 13D0000h-13DFFFFh 13C0000h-13CFFFFh 13B0000h-13BFFFFh 13A0000h-13AFFFFh 1390000h-139FFFFh 1380000h-138FFFFh 1370000h-137FFFFh 1360000h-136FFFFh 1350000h-135FFFFh 1340000h-134FFFFh 1330000h-133FFFFh 1320000h-132FFFFh 1310000h-131FFFFh 1300000h-130FFFFh 12F0000h-12FFFFFh 12E0000h-12EFFFFh 12D0000h-12DFFFFh 12C0000h-12CFFFFh 12B0000h-12BFFFFh 12A0000h-12AFFFFh 1290000h-129FFFFh 1280000h-128FFFFh 1270000h-127FFFFh 1260000h-126FFFFh 1250000h-125FFFFh 1240000h-124FFFFh 1230000h-123FFFFh 1220000h-122FFFFh 1210000h-121FFFFh 1200000h-120FFFFh Bank Block BA335 BA334 BA333 BA332 BA331 BA330 Bank 10 BA329 BA328 BA327 BA326 BA325 BA324 BA323 BA322 BA321 BA320 BA319 BA318 BA317 BA316 BA315 BA314 BA313 BA312 BA311 BA310 BA309 BA308 Bank 9 BA307 BA306 BA305 BA304 BA303 BA302 BA301 BA300 BA299 BA298 BA297 BA296 BA295 BA294 BA293 BA292 BA291 - 66 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 11F0000h-11FFFFFh 11E0000h-11EFFFFh 11D0000h-11DFFFFh 11C0000h-11CFFFFh 11B0000h-11BFFFFh 11A0000h-11AFFFFh 1190000h-119FFFFh 1180000h-118FFFFh 1170000h-117FFFFh 1160000h-116FFFFh 1150000h-115FFFFh 1140000h-114FFFFh 1130000h-113FFFFh 1120000h-112FFFFh 1110000h-111FFFFh 1100000h-110FFFFh 10F0000h-10FFFFFh 10E0000h-10EFFFFh 10D0000h-10DFFFFh 10C0000h-10CFFFFh 10B0000h-10BFFFFh 10A0000h-10AFFFFh 1090000h-109FFFFh 1080000h-108FFFFh 1070000h-107FFFFh 1060000h-106FFFFh 1050000h-105FFFFh 1040000h-104FFFFh 1030000h-103FFFFh 1020000h-102FFFFh 1010000h-101FFFFh 1000000h-100FFFFh 0FF0000h-0FFFFFFh 0FE0000h-0FEFFFFh 0FD0000h-0FDFFFFh 0FC0000h-0FCFFFFh 0FB0000h-0FBFFFFh 0FA0000h-0FAFFFFh 0F90000h-0F9FFFFh 0F80000h-0F8FFFFh 0F70000h-0F7FFFFh 0F60000h-0F6FFFFh 0F50000h-0F5FFFFh 0F40000h-0F4FFFFh 0F30000h-0F3FFFFh Bank Block BA290 BA289 BA288 BA287 BA286 BA285 BA284 BA283 BA282 BA281 BA280 BA279 BA278 BA277 BA276 Bank 8 BA275 BA274 BA273 BA272 BA271 BA270 BA269 BA268 BA267 BA266 BA265 BA264 BA263 BA262 BA261 BA260 BA259 BA258 BA257 BA256 BA255 BA254 BA253 Bank 7 BA252 BA251 BA250 BA249 BA248 BA247 BA246 - 67 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0F20000h-0F2FFFFh 0F10000h-0F1FFFFh 0F00000h-0F0FFFFh 0EF0000h-0EFFFFFh 0EE0000h-0EEFFFFh 0ED0000h-0EDFFFFh 0EC0000h-0ECFFFFh 0EB0000h-0EBFFFFh 0EA0000h-0EAFFFFh 0E90000h-0E9FFFFh 0E80000h-0E8FFFFh 0E70000h-0E7FFFFh 0E60000h-0E6FFFFh 0E50000h-0E5FFFFh 0E40000h-0E4FFFFh 0E30000h-0E3FFFFh 0E20000h-0E2FFFFh 0E10000h-0E1FFFFh 0E00000h-0E0FFFFh 0DF0000h-0DFFFFFh 0DE0000h-0DEFFFFh 0DD0000h-0DDFFFFh 0DC0000h-0DCFFFFh 0DB0000h-0DBFFFFh 0DA0000h-0DAFFFFh 0D90000h-0D9FFFFh 0D80000h-0D8FFFFh 0D70000h-0D7FFFFh 0D60000h-0D6FFFFh 0D50000h-0D5FFFFh 0D40000h-0D4FFFFh 0D30000h-0D3FFFFh 0D20000h-0D2FFFFh 0D10000h-0D1FFFFh 0D00000h-0D0FFFFh 0CF0000h-0CFFFFFh 0CE0000h-0CEFFFFh 0CD0000h-0CDFFFFh 0CC0000h-0CCFFFFh 0CB0000h-0CBFFFFh 0CA0000h-0CAFFFFh 0C90000h-0C9FFFFh 0C80000h-0C8FFFFh 0C70000h-0C7FFFFh 0C60000h-0C6FFFFh Bank Block BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 Bank 7 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 BA220 BA219 BA218 BA217 BA216 BA215 Bank 6 BA214 BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 BA203 BA202 BA201 - 68 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0C50000h-0C5FFFFh 0C40000h-0C4FFFFh 0C30000h-0C3FFFFh 0C20000h-0C2FFFFh 0C10000h-0C1FFFFh 0C00000h-0C0FFFFh 0BF0000h-0BFFFFFh 0BE0000h-0BEFFFFh 0BD0000h-0BDFFFFh 0BC0000h-0BCFFFFh 0BB0000h-0BBFFFFh 0BA0000h-0BAFFFFh 0B90000h-0B9FFFFh 0B80000h-0B8FFFFh 0B70000h-0B7FFFFh 0B60000h-0B6FFFFh 0B50000h-0B5FFFFh 0B40000h-0B4FFFFh 0B30000h-0B3FFFFh 0B20000h-0B2FFFFh 0B10000h-0B1FFFFh 0B00000h-0B0FFFFh 0AF0000h-0AFFFFFh 0AE0000h-0AEFFFFh 0AD0000h-0ADFFFFh 0AC0000h-0ACFFFFh 0AB0000h-0ABFFFFh 0AA0000h-0AAFFFFh 0A90000h-0A9FFFFh 0A80000h-0A8FFFFh 0A70000h-0A7FFFFh 0A60000h-0A6FFFFh 0A50000h-0A5FFFFh 0A40000h-0A4FFFFh 0A30000h-0A3FFFFh 0A20000h-0A2FFFFh 0A10000h-0A1FFFFh 0A00000h-0A0FFFFh 09F0000h-09FFFFFh 09E0000h-09EFFFFh 09D0000h-09DFFFFh 09C0000h-09CFFFFh 09B0000h-09BFFFFh 09A0000h-09AFFFFh 0990000h-099FFFFh Bank Block BA200 BA199 Bank 6 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 BA180 Bank 5 BA179 BA178 BA177 BA176 BA175 BA174 BA173 BA172 BA171 BA170 BA169 BA168 BA167 BA166 BA165 BA164 BA163 BA162 BA161 BA160 Bank 4 BA159 BA158 BA157 BA156 - 69 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0980000h-098FFFFh 0970000h-097FFFFh 0960000h-096FFFFh 0950000h-095FFFFh 0940000h-094FFFFh 0930000h-093FFFFh 0920000h-092FFFFh 0910000h-091FFFFh 0900000h-090FFFFh 08F0000h-08FFFFFh 08E0000h-08EFFFFh 08D0000h-08DFFFFh 08C0000h-08CFFFFh 08B0000h-08BFFFFh 08A0000h08AFFFFh 0890000h-089FFFFh 0880000h-088FFFFh 0870000h-087FFFFh 0860000h-086FFFFh 0850000h-085FFFFh 0840000h-084FFFFh 0830000h-083FFFFh 0820000h-082FFFFh 0810000h-081FFFFh 0800000h-080FFFFh 07F0000h-07FFFFFh 07E0000h-07EFFFFh 07D0000h-07DFFFFh 07C0000h-07CFFFFh 07B0000h-07BFFFFh 07A0000h-07AFFFFh 0790000h-079FFFFh 0780000h-078FFFFh 0770000h-077FFFFh 0760000h-076FFFFh 0750000h-075FFFFh 0740000h-074FFFFh 0730000h-073FFFFh 0720000h-072FFFFh 0710000h-071FFFFh 0700000h-070FFFFh 06F0000h-06FFFFFh 06E0000h-06EFFFFh 06D0000h-06DFFFFh 06C0000h-06CFFFFh Bank Block BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 Bank 4 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124 BA123 BA122 Bank 3 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 - 70 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 06B0000h-06BFFFFh 06A0000h-06AFFFFh 0690000h-069FFFFh 0680000h-068FFFFh 0670000h-067FFFFh 0660000h-066FFFFh 0650000h-065FFFFh 0640000h-064FFFFh 0630000h-063FFFFh 0620000h-062FFFFh 0610000h-061FFFFh 0600000h-060FFFFh 05F0000h-05FFFFFh 05E0000h-05EFFFFh 05D0000h-05DFFFFh 05C0000h-05CFFFFh 05B0000h-05BFFFFh 05A0000h-05AFFFFh 0590000h-059FFFFh 0580000h-058FFFFh 0570000h-057FFFFh 0560000h-056FFFFh 0550000h-055FFFFh 0540000h-054FFFFh 0530000h-053FFFFh 0520000h-052FFFFh 0510000h-051FFFFh 0500000h-050FFFFh 04F0000h-04FFFFFh 04E0000h-04EFFFFh 04D0000h-04DFFFFh 04C0000h-04CFFFFh 04B0000h-04BFFFFh 04A0000h-04AFFFFh 0490000h-049FFFFh 0480000h-048FFFFh 0470000h-047FFFFh 0460000h-046FFFFh 0450000h-045FFFFh 0440000h-044FFFFh 0430000h-043FFFFh 0420000h-042FFFFh 0410000h-041FFFFh 0400000h-040FFFFh 03F0000h-03FFFFFh Bank Block BA110 BA109 BA108 BA107 BA106 Bank 3 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 BA84 Bank 2 BA83 BA82 BA81 BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 Bank 1 BA66 - 71 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 03E0000h-03EFFFFh 03D0000h-03DFFFFh 03C0000h-03CFFFFh 03B0000h-03BFFFFh 03A0000h-03AFFFFh 0390000h-039FFFFh 0380000h-038FFFFh 0370000h-037FFFFh 0360000h-036FFFFh 0350000h-035FFFFh 0340000h-034FFFFh 0330000h-033FFFFh 0320000h-032FFFFh 0310000h-031FFFFh 0300000h-030FFFFh 02F0000h-02FFFFFh 02E0000h-02EFFFFh 02D0000h-02DFFFFh 02C0000h-02CFFFFh 02B0000h-02BFFFFh 02A0000h-02AFFFFh 0290000h-029FFFFh 0280000h-028FFFFh 0270000h-027FFFFh 0260000h-026FFFFh 0250000h-025FFFFh 0240000h-024FFFFh 0230000h-023FFFFh 0220000h-022FFFFh 0210000h-021FFFFh 0200000h-020FFFFh 01F0000h-01FFFFFh 01E0000h-01EFFFFh 01D0000h-01DFFFFh 01C0000h-01CFFFFh 01B0000h-01BFFFFh 01A0000h-01AFFFFh 0190000h-019FFFFh 0180000h-018FFFFh 0170000h-017FFFFh 0160000h-016FFFFh 0150000h-015FFFFh 0140000h-014FFFFh 0130000h-013FFFFh 0120000h-012FFFFh Bank Block BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 Bank 1 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 Bank 0 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 - 72 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 16 kwords 16 kwords 16 kwords 16 kwords Rev. 1.0 MCP Memory (x16) Address Range 0110000h-011FFFFh 0100000h-010FFFFh 00F0000h-00FFFFFh 00E0000h-00EFFFFh 00D0000h-00DFFFFh 00C0000h-00CFFFFh 00B0000h-00BFFFFh 00A0000h-00AFFFFh 0090000h-009FFFFh 0080000h-008FFFFh 0070000h-007FFFFh 0060000h-006FFFFh 0050000h-005FFFFh 0040000h-004FFFFh 0030000h-003FFFFh 0020000h-002FFFFh 0010000h-001FFFFh 000C000h-000FFFFh 0008000h-000BFFFh 0004000h-0007FFFh 0000000h-0003FFFh Bank Block BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 Bank 0 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 [Table 19] Bottom Boot OTP Block Addresses OTP Block Address A24 ~ A8 00000h Block Size 512 words (x16) Address Range* 0000000h-00001FFh After entering OTP Block, any issued addresses should be in the range of OTP block address. - 73 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1FF0000h-1FFFFFFh 1FE0000h-1FEFFFFh 1FD0000h-1FDFFFFh 1FC0000h-1FCFFFFh 1FB0000h-1FBFFFFh 1FA0000h-1FAFFFFh 1F90000h-1F9FFFFh 1F80000h-1F8FFFFh 1F70000h-1F7FFFFh 1F60000h-1F6FFFFh 1F50000h-1F5FFFFh 1F40000h-1F4FFFFh 1F30000h-1F3FFFFh 1F20000h-1F2FFFFh 1F10000h-1F1FFFFh 1F00000h-1F0FFFFh 1EF0000h-1EFFFFFh 1EE0000h-1EEFFFFh 1ED0000h-1EDFFFFh 1EC0000h-1ECFFFFh 1EB0000h-1EBFFFFh 1EA0000h-1EAFFFFh 1E90000h-1E9FFFFh 1E80000h-1E8FFFFh 1E70000h-1E7FFFFh 1E60000h-1E6FFFFh 1E50000h-1E5FFFFh 1E40000h-1E4FFFFh 1E30000h-1E3FFFFh 1E20000h-1E2FFFFh 1E10000h-1E1FFFFh 1E00000h-1E0FFFFh 1DF0000h-1DFFFFFh 1DE0000h-1DEFFFFh 1DD0000h-1DDFFFFh 1DC0000h-1DCFFFFh 1DB0000h-1DBFFFFh 1DA0000h-1DAFFFFh 1D90000h-1D9FFFFh 1D80000h-1D8FFFFh 1D70000h-1D7FFFFh 1D60000h-1D6FFFFh [Table 20] Uniform Block Address Table Bank Block BA511 BA510 BA509 BA508 BA507 BA506 BA505 BA504 BA503 BA502 BA501 BA500 BA499 BA498 BA497 Bank 0 BA496 BA495 BA494 BA493 BA492 BA491 BA490 BA489 BA488 BA487 BA486 BA485 BA484 BA483 BA482 BA481 BA480 BA479 BA478 BA477 BA476 Bank 1 BA475 BA474 BA473 BA472 BA471 BA470 - 74 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1D50000h-1D5FFFFh 1D40000h-1D4FFFFh 1D30000h-1D3FFFFh 1D20000h-1D2FFFFh 1D10000h-1D1FFFFh 1D00000h-1D0FFFFh 1CF0000h-1CFFFFFh 1CE0000h-1CEFFFFh 1CD0000h-1CDFFFFh 1CC0000h-1CCFFFFh 1CB0000h-1CBFFFFh 1CA0000h-1CAFFFFh 1C90000h-1C9FFFFh 1C80000h-1C8FFFFh 1C70000h-1C7FFFFh 1C60000h-1C6FFFFh 1C50000h-1C5FFFFh 1C40000h-1C4FFFFh 1C30000h-1C3FFFFh 1C20000h-1C2FFFFh 1C10000h-1C1FFFFh 1C00000h-1C0FFFFh 1BF0000h-1BFFFFFh 1BE0000h-1BEFFFFh 1BD0000h-1BDFFFFh 1BC0000h-1BCFFFFh 1BB0000h-1BBFFFFh 1BA0000h-1BAFFFFh 1B90000h-1B9FFFFh 1B80000h-1B8FFFFh 1B70000h-1B7FFFFh 1B60000h-1B6FFFFh 1B50000h-1B5FFFFh 1B40000h-1B4FFFFh 1B30000h-1B3FFFFh 1B20000h-1B2FFFFh 1B10000h-1B1FFFFh 1B00000h-1B0FFFFh 1AF0000h-1AFFFFFh 1AE0000h-1AEFFFFh 1AD0000h-1ADFFFFh 1AC0000h-1ACFFFFh 1AB0000h-1ABFFFFh 1AA0000h-1AAFFFFh 1A90000h-1A9FFFFh Bank Block BA469 BA468 BA467 BA466 BA465 BA464 BA463 BA462 BA461 BA460 Bank 1 BA459 BA458 BA457 BA456 BA455 BA454 BA453 BA452 BA451 BA450 BA449 BA448 BA447 BA446 BA445 BA444 BA443 BA442 BA441 BA440 BA439 BA438 BA437 Bank 2 BA436 BA435 BA434 BA433 BA432 BA431 BA430 BA429 BA428 BA427 BA426 BA425 - 75 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1A80000h-1A8FFFFh 1A70000h-1A7FFFFh 1A60000h-1A6FFFFh 1A50000h-1A5FFFFh 1A40000h-1A4FFFFh 1A30000h-1A3FFFFh 1A20000h-1A2FFFFh 1A10000h-1A1FFFFh 1A00000h-1A0FFFFh 19F0000h-19FFFFFh 19E0000h-19EFFFFh 19D0000h-19DFFFFh 19C0000h-19CFFFFh 19B0000h-19BFFFFh 19A0000h-19AFFFFh 1990000h-199FFFFh 1980000h-198FFFFh 1970000h-197FFFFh 1960000h-196FFFFh 1950000h-195FFFFh 1940000h-194FFFFh 1930000h-193FFFFh 1920000h-192FFFFh 1910000h-191FFFFh 1900000h-190FFFFh 18F0000h-18FFFFFh 18E0000h-18EFFFFh 18D0000h-18DFFFFh 18C0000h-18CFFFFh 18B0000h-18BFFFFh 18A0000h-18AFFFFh 1890000h-189FFFFh 1880000h-188FFFFh 1870000h-187FFFFh 1860000h-186FFFFh 1850000h-185FFFFh 1840000h-184FFFFh 1830000h-183FFFFh 1820000h-182FFFFh 1810000h-181FFFFh 1800000h-180FFFFh 17F0000h-17FFFFFh 17E0000h-17EFFFFh 17D0000h-17DFFFFh 17C0000h-17CFFFFh Bank Block BA424 BA423 BA422 BA421 Bank 2 BA420 BA419 BA418 BA417 BA416 BA415 BA414 BA413 BA412 BA411 BA410 BA409 BA408 BA407 BA406 BA405 BA404 BA403 BA402 BA401 Bank 3 BA400 BA399 BA398 BA397 BA396 BA395 BA394 BA393 BA392 BA391 BA390 BA389 BA388 BA387 BA386 BA385 BA384 BA383 Bank 4 BA382 BA381 BA380 - 76 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 17B0000h-17BFFFFh 17A0000h-17AFFFFh 1790000h-179FFFFh 1780000h-178FFFFh 1770000h-177FFFFh 1760000h-176FFFFh 1750000h-175FFFFh 1740000h-174FFFFh 1730000h-173FFFFh 1720000h-172FFFFh 1710000h-171FFFFh 1700000h-170FFFFh 16F0000h-16FFFFFh 16E0000h-16EFFFFh 16D0000h-16DFFFFh 16C0000h-16CFFFFh 16B0000h-16BFFFFh 16A0000h-16AFFFFh 1690000h-169FFFFh 1680000h-168FFFFh 1670000h-167FFFFh 1660000h-166FFFFh 1650000h-165FFFFh 1640000h-164FFFFh 1630000h-163FFFFh 1620000h-162FFFFh 1610000h-161FFFFh 1600000h-160FFFFh 15F0000h-15FFFFFh 15E0000h-15EFFFFh 15D0000h-15DFFFFh 15C0000h-15CFFFFh 15B0000h-15BFFFFh 15A0000h-15AFFFFh 1590000h-159FFFFh 1580000h-158FFFFh 1570000h-157FFFFh 1560000h-156FFFFh 1550000h-155FFFFh 1540000h-154FFFFh 1530000h-153FFFFh 1520000h-152FFFFh 1510000h-151FFFFh 1500000h-150FFFFh Bank Block BA379 BA378 BA377 BA376 BA375 BA374 BA373 BA372 BA371 BA370 BA369 BA368 BA367 Bank 4 BA366 BA365 BA364 BA363 BA362 BA361 BA360 BA359 BA358 BA357 BA356 BA355 BA354 BA353 BA352 BA351 BA350 BA349 BA348 BA347 BA346 BA345 Bank5 BA344 BA343 BA342 BA341 BA340 BA339 BA338 BA337 BA336 - 77 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 14F0000h-14FFFFFh 14E0000h-14EFFFFh 14D0000h-14DFFFFh 14C0000h-14CFFFFh 14B0000h-14BFFFFh 14A0000h-14AFFFFh 1490000h-149FFFFh 1480000h-148FFFFh 1470000h-147FFFFh 1460000h-146FFFFh 1450000h-145FFFFh 1440000h-144FFFFh 1430000h-143FFFFh 1420000h-142FFFFh 1410000h-141FFFFh 1400000h-140FFFFh 13F0000h-13FFFFFh 13E0000h-13EFFFFh 13D0000h-13DFFFFh 13C0000h-13CFFFFh 13B0000h-13BFFFFh 13A0000h-13AFFFFh 1390000h-139FFFFh 1380000h-138FFFFh 1370000h-137FFFFh 1360000h-136FFFFh 1350000h-135FFFFh 1340000h-134FFFFh 1330000h-133FFFFh 1320000h-132FFFFh 1310000h-131FFFFh 1300000h-130FFFFh 12F0000h-12FFFFFh 12E0000h-12EFFFFh 12D0000h-12DFFFFh 12C0000h-12CFFFFh 12B0000h-12BFFFFh 12A0000h-12AFFFFh 1290000h-129FFFFh 1280000h-128FFFFh 1270000h-127FFFFh 1260000h-126FFFFh 1250000h-125FFFFh 1240000h-124FFFFh 1230000h-123FFFFh Bank Block BA335 BA334 BA333 BA332 BA331 BA330 BA329 Bank 5 BA328 BA327 BA326 BA325 BA324 BA323 BA322 BA321 BA320 BA319 BA318 BA317 BA316 BA315 BA314 BA313 BA312 BA311 BA310 BA309 BA308 BA307 BA306 Bank 6 BA305 BA304 BA303 BA302 BA301 BA300 BA299 BA298 BA297 BA296 BA295 BA294 BA293 BA292 BA291 - 78 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1220000h-122FFFFh 1210000h-121FFFFh 1200000h-120FFFFh 11F0000h-11FFFFFh 11E0000h-11EFFFFh 11D0000h-11DFFFFh 11C0000h-11CFFFFh 11B0000h-11BFFFFh 11A0000h-11AFFFFh 1190000h-119FFFFh 1180000h-118FFFFh 1170000h-117FFFFh 1160000h-116FFFFh 1150000h-115FFFFh 1140000h-114FFFFh 1130000h-113FFFFh 1120000h-112FFFFh 1110000h-111FFFFh 1100000h-110FFFFh 10F0000h-10FFFFFh 10E0000h-10EFFFFh 10D0000h-10DFFFFh 10C0000h-10CFFFFh 10B0000h-10BFFFFh 10A0000h-10AFFFFh 1090000h-109FFFFh 1080000h-108FFFFh 1070000h-107FFFFh 1060000h-106FFFFh 1050000h-105FFFFh 1040000h-104FFFFh 1030000h-103FFFFh Bank Block BA290 Bank 6 BA289 BA288 BA287 BA286 BA285 BA284 BA283 BA282 BA281 BA280 BA279 BA278 BA277 BA276 BA275 BA274 Bank 7 BA273 BA272 BA271 BA270 BA269 BA268 BA267 BA266 BA265 BA264 BA263 BA262 BA261 BA260 BA259 - 79 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 1020000h-102FFFFh 1010000h-101FFFFh 1000000h-100FFFFh 0FF0000h-0FFFFFFh 0FE0000h-0FEFFFFh 0FD0000h-0FDFFFFh 0FC0000h-0FCFFFFh 0FB0000h-0FBFFFFh 0FA0000h-0FAFFFFh 0F90000h-0F9FFFFh 0F80000h-0F8FFFFh 0F70000h-0F7FFFFh 0F60000h-0F6FFFFh 0F50000h-0F5FFFFh 0F40000h-0F4FFFFh 0F30000h-0F3FFFFh 0F20000h-0F2FFFFh 0F10000h-0F1FFFFh 0F00000h-0F0FFFFh 0EF0000h-0EFFFFFh 0EE0000h-0EEFFFFh 0ED0000h-0EDFFFFh 0EC0000h-0ECFFFFh 0EB0000h-0EBFFFFh 0EA0000h-0EAFFFFh 0E90000h-0E9FFFFh 0E80000h-0E8FFFFh 0E70000h-0E7FFFFh 0E60000h-0E6FFFFh 0E50000h-0E5FFFFh 0E40000h-0E4FFFFh 0E30000h-0E3FFFFh 0E20000h-0E2FFFFh 0E10000h-0E1FFFFh 0E00000h-0E0FFFFh 0DF0000h-0DFFFFFh 0DE0000h-0DEFFFFh 0DD0000h-0DDFFFFh 0DC0000h-0DCFFFFh 0DB0000h-0DBFFFFh 0DA0000h-0DAFFFFh 0D90000h-0D9FFFFh 0D80000h-0D8FFFFh 0D70000h-0D7FFFFh 0D60000h-0D6FFFFh Bank Block BA258 Bank 7 BA257 BA256 BA255 BA254 BA253 BA252 BA251 BA250 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 Bank 8 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 BA220 Bank 9 BA219 BA218 BA217 BA216 BA215 BA214 - 80 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0D50000h-0D5FFFFh 0D40000h-0D4FFFFh 0D30000h-0D3FFFFh 0D20000h-0D2FFFFh 0D10000h-0D1FFFFh 0D00000h-0D0FFFFh 0CF0000h-0CFFFFFh 0CE0000h-0CEFFFFh 0CD0000h-0CDFFFFh 0CC0000h-0CCFFFFh 0CB0000h-0CBFFFFh 0CA0000h-0CAFFFFh 0C90000h-0C9FFFFh 0C80000h-0C8FFFFh 0C70000h-0C7FFFFh 0C60000h-0C6FFFFh 0C50000h-0C5FFFFh 0C40000h-0C4FFFFh 0C30000h-0C3FFFFh 0C20000h-0C2FFFFh 0C10000h-0C1FFFFh 0C00000h-0C0FFFFh 0BF0000h-0BFFFFFh 0BE0000h-0BEFFFFh 0BD0000h-0BDFFFFh 0BC0000h-0BCFFFFh 0BB0000h-0BBFFFFh 0BA0000h-0BAFFFFh 0B90000h-0B9FFFFh 0B80000h-0B8FFFFh 0B70000h-0B7FFFFh 0B60000h-0B6FFFFh 0B50000h-0B5FFFFh 0B40000h-0B4FFFFh 0B30000h-0B3FFFFh 0B20000h-0B2FFFFh 0B10000h-0B1FFFFh 0B00000h-0B0FFFFh 0AF0000h-0AFFFFFh 0AE0000h-0AEFFFFh 0AD0000h-0ADFFFFh 0AC0000h-0ACFFFFh 0AB0000h-0ABFFFFh 0AA0000h-0AAFFFFh 0A90000h-0A9FFFFh Bank Block BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 Bank 9 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 Bank 10 BA180 BA179 BA178 BA177 BA176 BA175 BA174 BA173 BA172 BA171 BA170 BA169 - 81 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0A80000h-0A8FFFFh 0A70000h-0A7FFFFh 0A60000h-0A6FFFFh 0A50000h-0A5FFFFh 0A40000h-0A4FFFFh 0A30000h-0A3FFFFh 0A20000h-0A2FFFFh 0A10000h-0A1FFFFh 0A00000h-0A0FFFFh 09F0000h-09FFFFFh 09E0000h-09EFFFFh 09D0000h-09DFFFFh 09C0000h-09CFFFFh 09B0000h-09BFFFFh 09A0000h-09AFFFFh 0990000h-099FFFFh 0980000h-098FFFFh 0970000h-097FFFFh 0960000h-096FFFFh 0950000h-095FFFFh 0940000h-094FFFFh 0930000h-093FFFFh 0920000h-092FFFFh 0910000h-091FFFFh 0900000h-090FFFFh 08F0000h-08FFFFFh 08E0000h-08EFFFFh 08D0000h-08DFFFFh 08C0000h-08CFFFFh 08B0000h-08BFFFFh 08A0000h-08AFFFFh 0890000h-089FFFFh 0880000h-088FFFFh 0870000h-087FFFFh 0860000h-086FFFFh 0850000h-085FFFFh 0840000h-084FFFFh 0830000h-083FFFFh 0820000h-082FFFFh 0810000h-081FFFFh 0800000h-080FFFFh 07F0000h-07FFFFFh 07E0000h-07EFFFFh 07D0000h-07DFFFFh 07C0000h-07CFFFFh Bank Block BA168 BA167 BA166 BA165 Bank 10 BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 Bank 11 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 Bank 12 BA126 BA125 BA124 - 82 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 07B0000h-07BFFFFh 07A0000h-07AFFFFh 0790000h-079FFFFh 0780000h-078FFFFh 0770000h-077FFFFh 0760000h-076FFFFh 0750000h-075FFFFh 0740000h-074FFFFh 0730000h-073FFFFh 0720000h-072FFFFh 0710000h-071FFFFh 0700000h-070FFFFh 06F0000h-06FFFFFh 06E0000h-06EFFFFh 06D0000h-06DFFFFh 06C0000h-06CFFFFh 06B0000h-06BFFFFh 06A0000h-06AFFFFh 0690000h-069FFFFh 0680000h-068FFFFh 0670000h-067FFFFh 0660000h-066FFFFh 0650000h-065FFFFh 0640000h-064FFFFh 0630000h-063FFFFh 0620000h-062FFFFh 0610000h-061FFFFh 0600000h-060FFFFh 05F0000h-05FFFFFh 05E0000h-05EFFFFh 05D0000h-05DFFFFh 05C0000h-05CFFFFh 05B0000h-05BFFFFh 05A0000h-05AFFFFh 0590000h-059FFFFh 0580000h-058FFFFh 0570000h-057FFFFh 0560000h-056FFFFh 0550000h-055FFFFh 0540000h-054FFFFh 0530000h-053FFFFh 0520000h-052FFFFh 0510000h-051FFFFh 0500000h-050FFFFh Bank Block BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 Bank 12 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 Bank13 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80 - 83 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 04F0000h-04FFFFFh 04E0000h-04EFFFFh 04D0000h-04DFFFFh 04C0000h-04CFFFFh 04B0000h-04BFFFFh 04A0000h-04AFFFFh 0490000h-049FFFFh 0480000h-048FFFFh 0470000h-047FFFFh 0460000h-046FFFFh 0450000h-045FFFFh 0440000h-044FFFFh 0430000h-043FFFFh 0420000h-042FFFFh 0410000h-041FFFFh 0400000h-040FFFFh 03F0000h-03FFFFFh 03E0000h-03EFFFFh 03D0000h-03DFFFFh 03C0000h-03CFFFFh 03B0000h-03BFFFFh 03A0000h-03AFFFFh 0390000h-039FFFFh 0380000h-038FFFFh 0370000h-037FFFFh 0360000h-036FFFFh 0350000h-035FFFFh 0340000h-034FFFFh 0330000h-033FFFFh 0320000h-032FFFFh 0310000h-031FFFFh 0300000h-030FFFFh 02F0000h-02FFFFFh 02E0000h-02EFFFFh 02D0000h-02DFFFFh 02C0000h-02CFFFFh 02B0000h-02BFFFFh 02A0000h-02AFFFFh 0290000h-029FFFFh 0280000h-028FFFFh 0270000h-027FFFFh 0260000h-026FFFFh 0250000h-025FFFFh 0240000h-024FFFFh 0230000h-023FFFFh Bank Block BA79 BA78 BA77 BA76 BA75 BA74 BA73 Bank 13 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 Bank 14 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 - 84 - K5N1229ACD-BQ12 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 MCP Memory (x16) Address Range 0220000h-022FFFFh 0210000h-021FFFFh 0200000h-020FFFFh 01F0000h-01FFFFFh 01E0000h-01EFFFFh 01D0000h-01DFFFFh 01C0000h-01CFFFFh 01B0000h-01BFFFFh 01A0000h-01AFFFFh 0190000h-019FFFFh 0180000h-018FFFFh 0170000h-017FFFFh 0160000h-016FFFFh 0150000h-015FFFFh 0140000h-014FFFFh 0130000h-013FFFFh 0120000h-012FFFFh 0110000h-011FFFFh 0100000h-010FFFFh 00F0000h-00FFFFFh 00E0000h-00EFFFFh 00D0000h-00DFFFFh 00C0000h-00CFFFFh 00B0000h-00BFFFFh 00A0000h-00AFFFFh 0090000h-009FFFFh 0080000h-008FFFFh 0070000h-007FFFFh 0060000h-006FFFFh 0050000h-005FFFFh 0040000h-004FFFFh 0030000h-003FFFFh 0020000h-002FFFFh 0010000h-001FFFFh 0000000h-000FFFFh Bank Block BA34 Bank 14 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 Bank 15 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 [Table 21] Uniform OTP Block Addresses OTP Block Address A24 ~ A8 1FFFFh Block Size 512 words (x16) Address Range* 1FFFE00h-1FFFFFFh After entering OTP Block, any issued addresses should be in the range of OTP block address. - 85 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 128Mb (8M x16) Mux UtRAM2 C-die - 86 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 1.0 POWER UP SEQUENCE After VCC and VCCQ reach minimum operating voltage(1.7V), drive CS High. Then the device gets into the Power Up mode. Wait for minimum 150s to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the appropriate device operation, be sure to keep the following power up sequence. Asynch. mode is default mode and is set up after power up. ~ VCC VCC(Min) VCCQ(Min) ~ VCCQ 150us CS Min. 0ns CRE FIX "LOW" - 87 - K5N1229ACD-BQ12 datasheet Item Symbol VIN, VOUT VCC, VCCQ PD TSTG TA Ratings Rev. 1.0 MCP Memory 2.0 ABSOLUTE MAXIMUM RATINGS Unit V V W C C Voltage on any pin relative to Vss Power supply voltage relative to Vss Power Dissipation Storage temperature Operating Temperature -0.2 to VCCQ+0.3V -0.2 to 2.5V 1.0 -55 to 150 -25 to 85 NOTE : 1) Stresses greater than "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. 3.0 RECOMMENDED DC OPERATING CONDITIONS Item Power supply voltage(Core) Power supply voltage(I/O) Ground Input high voltage Input low voltage Symbol VCC VCCQ VSS, VSSQ VIH VIL Min 1.7 1.7 0 VCCQ-0.4 -0.23) Typ 1.8 1.8 0 Max 1.95 1.95 0 VCCQ+0.22) 0.4 Unit V V V V V NOTE : 1) TA= -25 to 85C, otherwise specified. 2) Overshoot: VCCQ +1.0V in case of pulse width 20ns. Overshoot is sampled, not 100% tested. 3) Undershoot: -1.0V in case of pulse width 20ns. Undershoot is sampled, not 100% tested. 4.0 CAPACITANCE Item Input capacitance Input/Output capacitance NOTE : 1) Freq.=1MHz, TA=25C 2) Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 6 6 Unit pF pF - 88 - K5N1229ACD-BQ12 datasheet Symbol ILI ILO ICC2 6) ICC3I 108Mhz ICC3R ICC3W ICC3I VIN=VSS to VCCQ CS=VIH, CRE=VIL, OE=VIH or WE=VIL, VIO=VSS to VCCQ Cycle time=min tRC/min tWC, IIO=0mA4), 100% duty, CS=VIL, CRE=VIL, VIN=VIL or VIH Test Conditions Rev. 1.0 MCP Memory 5.0 DC AND OPERATING CHARACTERISTICS Item Input Leakage Current Output Leakage Current Average Operating Current (Async) Min -2 -5 VIN = VCCQ or 0V CS=VIL, IIO=0mA4) IOL=0.2mA IOH=-0.2mA CS and ADV=VCCQ, CRE=0V, Other inputs=0V or VCCQ (Toggle is not allowed) 5) < 40C < 85C 1/2 Block < 40C Partial Refresh Current ISBP 2) CS and ADV=VCCQ, CRE=0V, Other inputs=0V or VCCQ (Toggle is not allowed) 5) < 85C 1/4 Block 1/8 Block 1/2 Block 1/4 Block 1/8 Block NOTE : 1) ISB1 is measured after 500ms after CS high. CLK should be fixed at high or at Low. 2) Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1). 3) Internal TCSR (Temperature Compensated Self Refresh) is used to optimize refresh cycle below 40C. 4) IIO=0mA; This parameter is specified with the outputs disabled to avoid external loading effects. 5) VIN=0V; all inputs should not be toggle. 6) This parameter is for page disable mode, Clock should not be inserted between ADV low and WE low during Write operation. Typ - Max 2 5 30 30 40 35 30 40 35 30 40 35 0.2 160 200 150 140 130 180 175 170 Unit A A mA mA mA mA mA mA mA mA mA mA V V A A Average Operating Current (Burst) 80Mhz ICC3R ICC3W ICC3I 66Mhz ICC3R ICC3W Output Low Voltage Output High Voltage Standby Current(CMOS) VOL VOH ISB11) 0.8xVCCQ - A A - 89 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.0 CRE (CONTROL REGISTER ENABLE) The configuration register values are written via A/DQ pins. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV, CS, or WE, whichever occurs first; LB and UB are "Don't Care." For reads, address inputs other than A[19:18] are "Don't Care," and register bits 15:0 are output as data (ADV HIGH) on A/DQ[15:0]. Immediately after performing a configuration register READ or WRITE operation, reading the memory array is highly recommended. 6.1 Bus Configuration Register The BCR defines how the device interacts with the system memory bus. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software sequence with A/DQ = 0001h on the third cycle. A19~A18 RS A/DQ15 OM A/DQ14 IL A/DQ13~A/DQ11 LC A/DQ10 WP A/DQ8 WC A/DQ5~A/DQ4 DS A/DQ3 BW A/DQ2~A/DQ0 BL Register Select A19 0 1 0 A18 0 0 1 RS RCR BCR DIDR A/DQ15 0 1 Operating Mode OM Synch. Asynch (default) 0 1 Initial Latency A/DQ14 IL Variable (default) Fixed A/DQ13 0 0 0 0 1 1 1 1 Latency Count A/DQ12 0 0 1 1 0 0 1 1 A/DQ11 0 1 0 1 0 1 0 1 LC Reserved Reserved 2 3 (default) 4 5 6 Reserved Wait Polarity A/ DQ10 0 1 WP Active Low Active High (default) Wait Config. A/ DQ8 0 1 WC at data 1 CLK prior (default) A/DQ5 0 0 1 1 Driver Strength A/ DQ4 0 1 0 1 DS Full Drive 1/2 Drive (default) 1/4 Drive 1/8 Drive Burst Wrap A/DQ3 0 1 BW Wrap No Wrap (default) A/ DQ2 0 0 0 1 1 Burst Length A/ DQ1 0 1 1 0 1 A/ DQ0 1 0 1 0 1 BL 4 word 8 word 16 word 32 word Continuous (default) NOTE : 1) A/DQ6, A/DQ7, A/DQ9, A16, A17, A20~A22 are reserved and should be '0' 2) The registers are set automatically to default value. 3) Refresh command will be denied during continuous operation. CS low should not be longer than tBC(tCSM max. 2.5us) 4) If the register code is invalid, register will be set to default value. - 90 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.2 Refresh Configuration Register The refresh configuration register (RCR) defines how the device performs its self refresh. Altering the refresh parameters can reduce current consumption during standby mode. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software sequence with A/DQ = 0000h on the third cycle. A19~A18 RS Register Select A19 0 1 0 A18 0 0 1 RS RCR BCR DIDR A/DQ2 0 0 0 0 1 1 1 1 NOTE : 1) A/DQ3, A/DQ5~A/DQ15, A16, A17, A20~A22 are reserved and should be '0' 2) The registers are set automatically to default value. A/DQ2~A/DQ0 PAR Partial Refresh A/DQ1 0 0 1 1 0 0 1 1 A/DQ0 0 1 0 1 0 1 0 1 PAR Full Array (default) Bottom 1/2 Array Bottom 1/4 Array Bottom 1/8 Array None of Array Top 1/2 Array Top 1/4 Array Top 1/8 Array 6.3 Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of 4, 8, 16, or 32 words or Continuous. 6.4 Burst Wrap (BCR[3]) Default = No Wrap The burst-wrap option determines if a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or steps through sequential addresses. [Table 1] Sequence and Burst Length Burst Wrap BCR[3] Wrap Starting Address Decimal 0 1 2 3 WRAP Yes ~ 7 ~ 15 ~ 31 0 1 2 3 No WRAP ~ No 7 ~ 15 ~ 31 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0- 1- 2- 3- 4- 5- 6 -7 1- 2- 3- 4- 5- 6- 7- 8 2- 3- 4- 5- 6- 7- 8- 9 3- 4- 5- 6- 7- 8- 9-10 ~ 7-8-9-10-11-12-13-14 0- 1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15 1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17-18 ~ 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22 ~ 15-16-17-18-19-20-21-22-23-24-25-26-27-28-29-30 4 word Burst Length Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 word Burst Length Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 ~ 7-0-1-2-3-4-5-6 16 word Burst Length Linear 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 ~ 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ~ 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 32 word Burst Length Linear 0 - 1 - 2 ~ 29-30-31 1 - 2 - 3 ~ 30-31 - 0 2 - 3 - 4 ~ 31 - 0 - 1 3-4-5~0-1-2 ~ 7-8-9 ~4-5-6 ~ Continuous Burst Linear 0-1-2-3-4-5 ~ 1-2-3-4-5-6 ~ 2-3-4-5-6-7 ~ 3-4-5-6-7-8 ~ ~ 7 - 8 - 9 - 10-11-12 ~ ~ 15-16-17 ~ 12- 13- 14 15-16-17-18-19-20 ~ ~ 31- 0 - 1 ~ 28-29-30 0 - 1 - 2 ~ 29-30-31 1 - 2 - 3 ~ 30-31-32 2 - 3 - 4 ~ 31-32-33 3 - 4 - 5 ~ 32-33-34 ~ 7 - 8 - 9 ~ 36-37-38 ~ 15-16-17 ~ 44-45-46 ~ 31-32-33 ~ 60-61-62 ~ 31-32-33-34-35-36 ~ 0-1-2-3-4-5 ~ 1-2-3-4-5-6 ~ 2-3-4-5-6-7 ~ 3-4-5-6-7-8 ~ ~ 7 - 8 - 9 - 10-11-12 ~ ~ 15-16-17-18-19-20 ~ ~ 31-32-33-34-35-36 ~ - 91 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.5 Drive Strength (BCR[5:4]) Default = 1/2 Drive Strength The optimization of output driver strength is possible to adjust for the different data loadings. The device can minimize the noise generated on the data bus during read operation. The device supports full, 1/2 and 1/4 driver strength. The device's default mode is 1/2 driver strength. Outputs are configured at 1/2 drive strength during testing. [Table 2] Drive Strength Driver Strength Impedance(typ.) Recommendation Full 25~30 CL = 30pF to 50pF 1/2 50 CL = 15pF to 30pF 108 MHz at light load 1/4 100 CL = 15pF or lower 1/8 TBD CL = 15pF or lower NOTE : 1) Impedance values are typical values, not 100% tested. 6.6 WAIT Configuration (BCR[8]) Default = 1 CLK Prior. The WAIT signal is output signal indicating the status of the data on the bus whether or not it is valid. WAIT configuration is to decide the timing when WAIT asserts or desserts. WAIT asserts (or desserts) one clock prior to the data when A/DQ8 is set to 1. (WAIT asserts (or desserts) at data clock when A/DQ8 is set to 0). WAIT polarity is to decide the WAIT signal level at which data is valid or invalid. Data is valid if WAIT signal is high when A/DQ10 is set to 0. (Data is valid if WAIT signal is low when A/DQ10 is set to 1). All the timing diagrams in this SPEC are illustrated based on following setup; A/DQ[10]:0 and A/DQ[8]:1. Below timing shows WAIT signal's movement when word boundary crossing happens in No-wrap mode 6.7 WAIT Polarity (BCR[10]) Default = Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pullup or pull-down resistor to maintain the de-asserted state. No-Wrap. Word-line Crossing. LATENCY : 2. WP : Low Enable 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 ADV Word-line Crossing period (Only exists in No-wrap mode or Continuous mode) A/DQ Valid Address D509 D510 D511 D512 D513 D514 D515 D516 D517 D518 1CLK 1CLK 1CLK WAIT A/DQ[8]:1 de-assertion assertion de-assertion WAIT A/DQ[8]:0 de-assertion assertion de-assertion Figure 1. WAIT Configuration During Burst Operation NOTE : 1)Non-default BCR setting: WAIT active LOW. 6.8 Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. 6.9 Latency Counter (BCR[13:11]) Default = 3 Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For allowable latency codes. - 92 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.10 Initial Access Latency (BCR[14]) Default = Variable Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter. [Table 3] Variable Latency Configuration Codes BCR[13:11] 010 011 Others Latency Configuration 2(3 clocks) 3(4 clocks)-default Reserved Latency Normal 2 3 Refresh Collision 4 6 Max Input CLK Frequency (MHz) 108 66(15ns) 108(9.26ns) 80 19,2ns 80(12.5ns) 66 40(25ns) 66(15ns) - [Table 4] Fixed Latency Configuration Codes BCR[13:11] 010 011 100 101 110 Others Latency Configuration 2 (3 clocks) 3 (4 clocks) 4 (5 clocks) 5 (6 clocks) 6 (7 clocks) Reserved Latency Count (N) 2 3 4 5 6 Max Input CLK Frequency (MHz) 108 33 (30ns) 52 (19.2ns) 66 (15ns) 80 (12.5ns) 108 (9.26ns) 80 20 (50ns) 40 (25ns) 52 (19.2ns) 66 (15ns) 80 (12.5ns) 66 20 (50ns) 33 (30ns) 40 (25ns) 52 (19.2ns) 66 (15ns) - NOTE : 1) Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle. CLK VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VALID ADDRESS Code 2 VALID ADDRESS Code 3 (Default) ADV A[22:16] A/DQ[15:0] VOH VOL Valid Output Valid Output Valid Output Valid Output Valid Output A/DQ[15:0] VALID ADDRESS Code 4 VALID ADDRESS VOH VOL Valid Output Valid Output Valid Output Valid Output A/DQ[15:0] VOH VOL Valid Output Valid Output Valid Output Don't Care Figure 2. Latency Counter (Variable Initial Latency, No Refresh Collision) Undefined - 93 - K5N1229ACD-BQ12 datasheet N-1 Cycles CLK VIH VIL VIH VIL VIH VIL VIH VIL tAA VIH VIL VIH VIL VALID ADDRESS VALID ADDRESS Rev. 1.0 MCP Memory N Cycle tAADV ADV A[22:16] tCO tACLK VOH VOL Valid Output Valid Output Valid Output Valid Output Valid Output CS A/DQ[15:0] (READ) A/DQ[15:0] (WRITE) tSP tHD Valid Input Valid Input Valid Input Valid Input Valid Input VALID ADDRESS Burst Identified (ADV = LOW) Don't Care Undefined Figure 3. Latency Counter (Fixed Latency) 6.11 Partial Array Refresh (RCR[2:0] Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. [Table 5] Address Patterns for PAR (RCR[4] = 1) RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1 Active Section Full Die One-half die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die Address Space 000000h-7FFFFFh 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 400000h-7FFFFFh 600000h-7FFFFFh 700000h-7FFFFFh Size 8 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 Density 128Mb 64Mb 32Mb 16Mb 0Mb 64Mb 32Mb 16Mb - 94 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.12 Device Identification Register The DIDR provides information on the device manufacturer, generation and the specific device configuration. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with A/DQ = 0002h on the third cycle. [Table 6] Device Identification Register Mapping Bit Field Field name DIDR[15] Row Length Length Options 512 words Bit Setting 1b DIDR[14:11] Device version Version 4th Bit Setting 0110 DIDR[10:8]) Device density Density 128Mb Bit Setting 011b DIDR[7:5] UtRAM generation Generation UtRAM2 Bit Setting 010b DIDR[4:0] Vendor ID Bit Setting 01100 CRE ADV A[22:16] (Except A[19:18]) A[19:18] tAVS tVP tAVH OPCODE ADDRESS Select Control Register ADDRESS Initiate control register access CS tCW OE tWP WE tCPH Write address bus value to control register LB/UB tAVS A/DQ[15:0] OPCODE tAVH ADDRESS Data Valid Don't Care Figure 4. Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation NOTE : 1) A[19:18] = 00b to load RCR, and 10b to load BCR. - 95 - K5N1229ACD-BQ12 datasheet 0 1 2 7 8 9 10 Rev. 1.0 MCP Memory CLK tSP CRE ADV A[22:16] (Except A[19:18]) A[19:18] tAS CS OE tSP WE LB/UB tSP A/DQ[15:0] tSP tHD tHD ADDRESS tAS OPCODE ADDRESS tCSP tHD tCPH tHD tHD Latch Control Register Address ADDRESS OPCODE DataValid Don't Care Figure 5. Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation NOTE : 1) Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: WAIT active LOW; WAIT asserted during delay. 2) A[19:18] = 00b to load RCR, and 10b to load BCR. 3) CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CS LOW cycles. CRE tAVS tAVH tAA ADV tVP tAVS tAVH tAAVD tLZ Address A[22:16] (Except A[19:18]) tAA A[19:18] Select Control Register Address tCO tCPH tHZ CS OE Initiate Register Access tOE WE LB/UB A/DQ[15:0] tOLZ tOHZ CR Valid Address DATA VALID Don't Care Figure 6. Register READ, Asynchronous Mode Followed by READ ARRAY Operation NOTE : 1) A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. Undefined - 96 - K5N1229ACD-BQ12 datasheet CLK tSP CRE ADV tSP tSP tHD tHD ADDRESS ADDRESS tABA tCBPH3 tHD Rev. 1.0 MCP Memory A[22:16] (Except A[19:18]) A[19:18] ADDRESS ADDRESS tCSP CS tHZ OE tBOE LB/UB tOLZ tKW WAIT High-Z tSP A/DQ[15:0] tHD CR Valid tKOH ADDRESS DATA VALID tOHZ tACLK High-Z ADDRESS Latch Control Register Address Don't Care Undefined Figure 7. Register READ, Synchronous Mode Followed by READ ARRAY Operation NOTE : 1) Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 3) CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CS LOW cycles. - 97 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 6.13 Software Access Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations. The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation. The address used during all READ and WRITE operations is the highest address of the device being accessed (3FFFFF); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access the DIDR. During the fourth operation, A/DQ[15:0] transfer data in to or out of bits 15-0 of the registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. READ CS READ WRITE WRITE OE tBSA WE tBHA LB/UB ADV ADDRESS XXXX (max) ADDRESS XXXX (max) ADDRESS (max) ADDRESS (max) CR VALID IN A/DQ[15:0] RCR: 0000h BCR: 0001h Don't Care Figure 8. Load Configuration Register NOTE : 1) /WE should be deasserted before /CS deasserting. READ CS READ WRITE READ OE WE LB/UB ADV A/DQ[15:0] ADDRESS XXXX (max) ADDRESS XXXX (max) ADDRESS (max) ADDRESS CR VALID (max) OUT RCR: 0000h BCR: 0001h DIDR: 0002h Don't Care Figure 9. Read Configuration Register NOTE : 1) /WE should be deasserted before /CS deasserting. 2) ALL Write Operation have tBSA, tBHA. - 98 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 7.0 BUS OPERATING MODES The bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. 7.1 Asynchronous Mode (default mode) 7.1.1 Asynchronous read operation Asynchronous read operation starts when CS, OE and UB or LB are asserted. ADV can be taken HIGH to capture the address. First data will be driven out of the A/DQ bus after random access time(tAA). WE should be de-asserted during read operation. The CLK input must be held static LOW during read operation. WAIT will be driven while the device is enabled and its state should be ignored. 7.1.2 Asynchronous write operation Asynchronous write operation starts when CS, WE and UB or LB are asserted. The data to be written is latched on the rising edge of CS, WE, or LB/UB (whichever occurs first). OE is High during write operation. WE LOW time must be limited to tCSM. The CLK input must be held static LOW during write operation. WAIT signal is Hi-Z. CS CS A[22:16] Address A[22:16] Address ADV ADV < tCSM OE WE LB/UB High-Z LB/UB A/DQ[15:0] Address DATA A/DQ[15:0] Address DATA Don't Care Undefined Figure 10. READ Operation WE = HIGH). Figure 11. WRITE Operation OE = HIGH) 7.2 Functional Description (Asynch. mode) Asynchfonous Mode BCR[15] = 1 Read Write Standby No operation Configuration register write Configuration register read Power Active Active Standby Idle Active Active CLK L L L L L L H X L ADV CS L L H L L L OE L H X X H L WE H L X X L CRE L L L L H H UB / LB L L X X X L WAIT Low-Z Low-Z High-Z Low-Z Low-Z Low-Z A/DQ[15:0] Data out Data in High-Z X High-Z Config. Reg.out Notes 1 1 2 1 H NOTE : 1) The device will consume active power in this mode whenever addresses are changed. 2) When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. - 99 - K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 8.0 Burst Mode Operation 8.1 synchronous Mode 8.1.1 Synchronous Burst Read Operation Burst Read command is implemented when ADV is detected low at clock rising edge. WE should be de-asserted. Burst operation re-starts whenever ADV is detected low at clock rising edge even in the middle of operation. 8.1.2 Synchronous Burst Write Operation Burst Write command is implemented when ADV & WE are detected low at clock rising edge. Burst Write operation re-starts whenever ADV is detected low at clock rising edge even in the middle of Burst Write operation. CLK CS ADV Latency Code 3 (4 clocks) A[22:16] OE WE WAIT LB/UB ADD. VALID ADD. VALID A/DQ[15:0] ADD. VALID D[0] D[1] D[2] D[3] ADD. VALID READ Burst Identified (WE = HIGH) Don't Care Undefined Figure 12. Burst Mode READ (4-word burst) NOTE : 1) Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; 2) Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay. 3) Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access. CLK CS ADV Latency Code 3 (4 clocks) A[22:16] WE WAIT LB/UB A/DQ[15:0] ADD. VALID ADD. VALID ADD. VALID D[0] D[1] D[2] D[3] ADD. VALID WRITE Burst Identified (WE = LOW) Don't Care Figure 13. Burst Mode WRITE (4-word burst) NOTE : 1) Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; 2) Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay. 3) tAS is need to Burst Write Operation. - 100 K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies. CLK A[22:16] ADV CS OE WE LB/UB WAIT A/DQ[15:0] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL High-Z Address Valid Address Valid VOH VOL D[0] D[1] D[2] D[3] Don't Care Undefined Additional WAIT states inserted to allow refresh completion. Figure 14. Refresh Collision During Variable-Latency READ Operation NOTE : 1) Non-default BCR settings for refresh collision during variable-latency READ operation: 2) Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 8.2 Functional Description (Synch. mode) Burst Mode BCR[15] = 0 Standby No operation Initial burst read Initial burst write Burst continue Burst suspend Configuration register write Configuration register read Power Standby Idle Active Active Active Active Active Active X CLK L L ADV H X L L H X L L CS H L L L L L L L OE X X X H X H H L WE X X H L X X L H CRE L L L L X X H H UB / LB X X L X L X X L WAIT High-Z Low-Z Low-Z Low-Z Low-Z Low-Z Low-Z Low-Z A/DQ[15:0] High-Z X Address Address Data in or Data out High-Z High-Z Config. reg.out 3 3 Notes 4 4 NOTE : 1) CLK must be LOW during async read and async write modes. 2) When LB and UB are in select mode (LOW), A/DQ[15:0] are affected. When only LB is in select mode, A/DQ[7:0] are affected. When only UB is in the select mode, A/ DQ[15:8] are affected. 3) The device will consume active power in this mode whenever addresses are changed. 4) When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. - 101 K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 8.3 Burst Suspend To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE should be taken HIGH to disable the outputs. otherwise, OE can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE is taken LOW, then CLK is restarted after valid data is available on the bus. The CS LOW time is limited by refresh considerations. CS must not stay LOW longer than tCSM. If a burst suspension will cause CS to remain LOW for longer than tCSM, CS should be taken HIGH and the burst restarted with a new CS LOW/ADV LOW cycle. 8.4 Boundary Crossing Continuous bursts or No wrap burst have the ability to start at a specified address and burst to the end of the address. It goes back to the first address and continues the burst operation. WAIT will be asserted at the boundary of the row and be desserted after crossing boundary of the row. There is no limitation for CS high time during Row Boundary Crossing. 8.5 WAIT Operation The WAIT output is typically connected to a shared systemlevel WAIT signal. The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that additional time is required before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into this device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. CS must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CS HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-asserts. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed. When the refresh operation has completed, the READ operation will continue normally. WAIT will be asserted but should be ignored during asynchronous READ and WRITE operations. By using fixed initial latency (BCR[14] = 1), this device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst. UtRAM2 WAIT READY WAIT Processor Other Device RDY Other Device External Pull-Up Pull-Down Resistor Figure 15. Wired or WAIT Configuration 8.6 LB / UB Operation The LB enable and UB enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle. The data to be written is latched on the rising edge of CS, WE whichever occurs first and LB, UB must have rising edge after CS or WE go high. LB and UB must be LOW during READ cycles. When both the LB and UB are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CS remains LOW. - 102 K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 9.0 LOW-POWER OPERATION 9.1 Temperature Compensated Self Refresh Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This UtRAM2 device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually adjusts the refresh rate to match that temperature. 9.2 Partial Array Refresh Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. 9.3 AC Input/Output Reference Waveform & AC Output Load Circuit VCCQ Input1 VSSQ NOTE : 1) AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns. 2) Input timing begins at VCCQ/2 and Output timing ends at VCCQ/2. 3) All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b) VccQ/22 Test Points VccQ/22 Output Test Points 50 VccQ/2 30pF DUT - 103 K5N1229ACD-BQ12 datasheet Symbol tAA tAADV tAVS tAVH tBA tBHZ tCSM tCSW tCPH tCO tCVS tHZ tOE tOHZ tOLZ tRC tVP 5 80 5 7 8 20 8 1 15 70 5 2 70 8 2.5 7.5 Min Max 70 70 Rev. 1.0 MCP Memory 10.0 TIMING REQUIREMENTS 10.1 Asynchronous READ Cycle Timing Requirements Parameter Address access time ADV access time Address setup to ADV HIGH Address hold from ADV HIGH LB/UB access time LB/UB disable to DQ High-Z output Maximum CS Pulse Width CS or ADV LOW to WAIT valid CS HIGH between subsequent Async Operations Chip select access time CS LOW to ADV HIGH Chip disable to DQ and WAIT High-Z output Output enable to valid output Output disable to DQ High-Z output Output ebable to Low-Z output READ cycle time ADV pulse width LOW Unit ns ns ns ns ns ns us ns ns ns ns ns ns ns ns ns ns 1 2 1 4 1 4 Notes 10.2 Asynchronous WRITE Cycle Timing Requirements Parameter Address setup to ADV going HIGH Address hold from ADV HIGH Address valid to end of WRITE LB/UB select to end of WRITE CS HIGH between subsequent async operations CS LOW to ADV HIGH Chip enable to end of WRITE Data HOLD from WRITE time Data WRITE setup time Chip disable to WAIT High-Z output End WRITE to Low-Z output ADV pulse width ADV setup to end of WRITE WRITE to DQ High-Z output CS or ADV LOW to WAIT valid WRITE pulse width WRITE recovery time /UB, /LB valid or mask setup time to beginning of write /UB, /LB valid or mask hold time to end of write Address Skew Symbol tAVS tAVH tAW tBW tCPH tCVS tCW tDH tDW tHZ tOW tVP tVS tWHZ tCSW tWP tWR tBSA tBHA tSKEW 1 55 0 0 0 10 5 5 70 8 7.5 Min 5 2 70 70 15 7 70 0 20 8 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 2 2 1 2 3 Notes NOTE : 1) The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2) The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 3) WE LOW time must be limited to tCSM (2.5s). 4) A refresh opportunity must be provided every tCSM. CS must not remain LOW longer than tCSM. - 104 K5N1229ACD-BQ12 datasheet Symbol tAA tAADV tACLK tBOE tCBPH tCSM tCSW tCLK tCO tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP tADVO tAVH tAHCR 5 3 3 2 2 2 2 3 8 5 3 4 2 2 3 2 8 1.6 7 2 2 4 8 5 3 5 2 2 1 9.26 70 4 2 8 1.8 9 2 2 5 15 2.5 7.5 1 12.5 70 5 2 108MHz Min Max 70 70 7 20 15 2.5 7.5 1 15 80MHz Min Max 70 70 9 20 15 Min Rev. 1.0 MCP Memory 10.3 Burst READ Cycle Timing Requirements Parameter Address access time (fixed latency) ADV access time (fixed latency) CLK to output delay Burst OE LOW to output delay CS HIGH between subsequent burst or operations Maximum CS pulse width LOW CS or ADV LOW to WAIT valid CLK period Chip select access time (fixed latency) CS setup time to active CLK edge Hold time from active CLK edge Chip desable to DQ and WAIT High-Z output CLK rise or fall time CLK to WAIT valid Output HOLD from CLK CLK HIGH or LOW time Output disable to DQ High-Z output Output enable to Low-Z output Setup time to active CLK edge ADV HIGH to OE LOW Address setup to ADV HIGH ADV HIGH to CLK Rising 66MHz Max 70 70 11 20 Unit ns ns ns ns ns 2.5 7.5 us ns ns 70 ns ns ns 8 2.0 11 ns ns ns ns ns 8 ns ns ns ns ns ns 1 2 1 4 3 3 Notes 4 4 10.4 Burst WRITE Cycle Timing Requirements Parameter CS HIGH between subseuent burst or mixed mode operations Maximum CS pulse width LOW CS LOW to WAIT valid Clock period CS setup to CLK active edge Hold time from active CLK edge Chip disable to WAIT High-Z output Last clock to ADV LOW (fixed latency) CLK rise or fall time Clock to WAIT valid CLK HIGH or LOW time Setup time to activate CLK edge Address Hold from ADV HIGH ADV HIGH to CLK Rising Symbol tCBPH tCSM tCSW tCLK tCSP tHD tHZ tKADV tKHKL tKHTL tKP tSP tAVH tAHCR 2 3 3 2 2 15 1.6 7 2 4 3 2 2 1 9.26 3 2 8 15 1.8 9 2 5 3 2 2 108MHz Min 15 2.5 7.5 1 12.5 4 2 8 15 2.0 11 Max 80MHz Min 15 2.5 7.5 1 15 5 2 8 Max 66MHz Min 15 2.5 7.5 Max Unit ns us ns ns ns ns ns ns ns ns ns ns ns ns 1 Notes 3 3 NOTE : 1) The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2) The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 3) A refresh opportunity must be provided every tCSM. CS must not remain LOW longer than tCSM. 4) tAA, tAADV, tCO guarantee at min set-up time. - 105 K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 11.0 TIMING DIAGRAMS 11.1 Asynchronous READ (CS controlled) tRC ADV VIH VIL tAADV tVP Valid Address tVP Valid Address A[22:16] VIH VIL tAVS tCVS tAVH tAVS tCPH tCVS tAVH CS VIH VIL VIH tCO tBA tHZ UB/ LB VIL tBHZ tOE VIH OE VIL tOLZ WE VIH VIL VIH VIL Valid Address tOHZ tOLZ tAA VOH VOL Valid output Valid Address VOH VOL A/DQ[15:0] tAVS tAVH tAVS tAVH Don't Care Undefined NOTE : 1) Don't care must be in VIL or VIH. 2) tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3) At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 4) tOE(max) is met only when OE becomes enabled after tAA(max). 5) If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to sustain standby state for min. tRC at least once in every 2.5us. 11.1.1 Address Skew for Asynchronous Operation ADDRESS ADDRESS tSKEW tSKEW tSKEW CS - 106 K5N1229ACD-BQ12 datasheet tRC Rev. 1.0 MCP Memory 11.2 Asynchronous READ (OE controlled) ADV VIH VIL tVP A[22:16] VIH VIL Valid Address tAADV tOEADV tVP Valid Address tAADV tAVS tCVS tAVH tAVS tAVH CS VIH VIL VIH tCO tBA tBHZ tOE UB/ LB VIL VIH OE VIL tOLZ WE VIH VIL VIH VIL Valid Address tOHZ tOLZ tAA VOH VOL Valid output Valid Address VOH VOL A/DQ[15:0] tAVS tAVH tAVS tAVH Undefined Don't Care NOTE : 1) Don't care must be in VIL or VIH. 2) tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3) At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 4) tOE(max) is met only when OE becomes enabled after tAA(max). 5) If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to sustain standby state for min. tRC at least once in every 2.5us. - 107 K5N1229ACD-BQ12 datasheet tVP Rev. 1.0 MCP Memory 11.3 Asynchronous READ Followed by Asynchronous WRITE (CS Controlled) ADV VIH VIL tAADV tVP tCVP tAVS tAVH A[22:16] VIH VIL Valid Address Valid Address tAVS tCVS tAVH tCPH tCW CS VIH VIL VIH tCO tBA tHZ tBSA tBHA UB/ LB VIL tOE VIH OE VIL tBHZ tOLZ WE VIH VIL tOHZ tWP tAA A/DQ[15:0] VIH VIL Valid Address VOH VOL Valid output tAW Valid Address Data Valid tAVS tAVH tAVS tAVH tDW tDH Don't Care Undefined - 108 K5N1229ACD-BQ12 datasheet tVP Rev. 1.0 MCP Memory 11.4 Asynchronous READ Followed by Asynchronous WRITE (OE, WE Controlled) ADV VIH VIL tAADV tVP tOEADV tAVS tAVH A[22:16] VIH VIL Valid Address Valid Address tAVS tCVS tAVH CS VIH VIL VIH tCO tBA tBSA tBHA UB/ LB VIL tOE VIH OE VIL tBHZ tOLZ WE VIH VIL tOHZ tWP tAA A/DQ[15:0] VIH VIL Valid Address VOH VOL Valid output tAW Valid Address Data Valid tAVS tAVH tAVS tAVH tDW tDH Don't Care Undefined - 109 K5N1229ACD-BQ12 datasheet tVP Rev. 1.0 MCP Memory 11.5 Asynchronous READ Followed by Asynchrous WRITE (UB, LB Controlled) ADV VIH VIL tAADV tVP tOEADV tAVS tAVH A[22:16] VIH VIL Valid Address Valid Address tAVS tCVS tAVH CS VIH VIL VIH tCO tBA tBSA tBHA UB/ LB VIL tOE VIH OE VIL tBHZ tOLZ WE VIH VIL tOHZ tWP tAA A/DQ[15:0] VIH VIL Valid Address VOH VOL Valid output Valid Address tAW Data Valid tAVS tAVH tAVS tAVH tDW tDH Don't Care Undefined - 110 K5N1229ACD-BQ12 datasheet Rev. 1.0 MCP Memory 11.6 Asynchronous READ Followed by WRITE at the Same Address (UB/LB Controlled) A[22:16] VIH VIL Valid Address tAVS tAADV tVP tBA tBSA tBHA ADV VIH VIL LB/UB VIH VIL tCVS VIH VIL VIH VIL VIH VIL tAVS tAVH VOH VOL tAA tDW tDH VIH VIL tOLZ tWP tCO tOE tBHZ tOHZ CS OE WE A/DQ[15:0] VIH IN/OUT VIL Valid Address Valid Output Valid Input Don't Care Undefined NOTE : 1) Don't care must be in VIL or VIH. - 111 K5N1229ACD-BQ12 datasheet tCLK VIH VIL VIH VIL VIH tSP tHD Rev. 1.0 MCP Memory 11.7 Single-Access Burst READ Operation--Variable Latency CLK ADV tSP tHD A[22:16] VIL VIH VIL Valid Address tCSP tAVH tAHCR tADVO tBOE tOHZ tHD tHZ CS OE VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL tCSW High-Z tSP tHD tOLZ WE tSP tKHTL tHD LB/UB WAIT High-Z tSP tHD VOH VOL tACLK tKOH Valid Output High-Z A/DQ[15:0] Valid Address READ Burst Identified (WE = HIGH) Don't Care Undefined NOTE : 1) Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) Don't care must be in VIL or VIH. - 112 K5N1229ACD-BQ12 datasheet tCLK tKHKL tKP tKP Rev. 1.0 MCP Memory 11.8 4-Word Burst READ Operation--Variable Latency VIH VIL tSP ADV VIH VIL tSP A[22:16] VIH VIL VIH VIL tCSP CS VIH VIL VIH VIL tSP WE VIH VIL VOH VOL tSP A/DQ[15:0] VIH VIL tHD VOH Valid Address CLK tHD tHD Valid Address tSP tAVH tAHCR tHD LB/UB tHD tCSM tADVO tBOE tCBPH tHZ OE tOHZ tHD tKHTL tCSW High-Z WAIT tKOH tACLK VOL Valid Output Valid Output Valid Output Valid Output High-Z READ Burst Identified (WE = HIGH) Don't Care Undefined NOTE : 1) Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) Don't care must be in VIL or VIH. - 113 K5N1229ACD-BQ12 datasheet tCLK VIH VIL VIH VIL tSP tHD tAHCR Rev. 1.0 MCP Memory 11.9 Single-Access Burst READ Operation--Fixed Latency CLK ADV tSP tHD A[22:16] VIH VIL Valid Address tCSP tAVH tHD tHZ CS VIH VIL tADVO OE VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL tCSW High-Z tBOE tOHZ tSP tHD tOLZ WE tSP tKHTL tHD LB/UB WAIT tSP tHD High-Z tACLK tKOH A/DQ[15:0] Valid Address Valid Output READ Burst Identified (WE = HIGH) Don't Care Undefined NOTE : 1) Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay. 2) Don't care must be in VIL or VIH. - 114 K5N1229ACD-BQ12 datasheet tCLK tKHKL tKP tKP Rev. 1.0 MCP Memory 11.10 4-Word Burst READ Operation--Fixed Latency VIH VIL tSP ADV VIH VIL tAHCR tAADV VIH A[22:16] VIL VIH LB/UB VIL tCSP CS VIH VIL VIH VIL tSP WE VIH VIL VOH VOL tSP A/DQ[15:0] IN/OUT VIH VIL tAA tHD tACLK Valid Output Valid Output Valid Output Valid Output High-Z CLK tHD Valid Address tSP tAVH tCSM tCO tADVO tHD tCBPH tBOE tHZ OE tOLZ tHD tKHTL tOHZ tCSW High-Z WAIT tKOH VOH VOL Valid Address READ Burst Identified (WE = HIGH) Don't Care Undefined NOTE : 1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) Don't care must be in VIL or VIH. - 115 K5N1229ACD-BQ12 datasheet tCLK tKHKL tKP tKP Rev. 1.0 MCP Memory 11.11 4-Word Burst READ Operation - Row Boundary Crossing CLK VIH VIL tSP ADV VIH VIL tAHCR tAADV VIH A[22:16] VIL VIH LB/UB VIL tCSP CS VIH VIL VIH VIL tSP WE VIH VIL VOH VOL tSP A/DQ[15:0] IN/OUT VIH VIL tAA tHD tACLK Valid Output Valid Output Valid Output Valid Output High-Z tHD Valid Address tAVH tSP tCSM tCO tADVO tHD tCBPH tBOE tHZ OE tOLZ tHD tKHTL tOHZ tCSW High-Z WAIT tKOH VOH VOL Valid Address READ Burst Identified (WE = HIGH) End of Row Don't Care Undefined NOTE : 1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) Don't care must be in VIL or VIH. 3) There is no limitation for CS high time during Row Boundary Crossing. 4) There is no ADV low during Row Boundary Crossing. - 116 K5N1229ACD-BQ12 datasheet tCLK NOTE 2 Rev. 1.0 MCP Memory 11.12 READ Burst Suspend VIH CLK VIL ADV VIH VIL tSP VIH A[22:16] VIL VIH VIL VIH VIL VIH VIL VIH VIL tCSW WAIT VOH VOL tSP A/DQ[15:0] VIH VIL tHD Valid Output Valid Output Valid Output Valid Output tSP tHD tADVO tAHCR tHD Valid Address Valid Address tCSP tCSM tHZ CS tOHZ tSP tHD NOTE 3 tOHZ OE WE LB/UB tBOE tOLZ tCSW High-Z tKOH tOLZ High-Z Valid Address tBOE Valid Output Valid Output Valid Address tACLK Don't Care Undefined NOTE : 1) Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend. 3) OE can stay LOW during burst suspend. If OE is LOW, A/DQ[15:0] will continue to output valid data. 4) Don't care must be in VIL or VIH. - 117 K5N1229ACD-BQ12 datasheet tVS tVP tVP Rev. 1.0 MCP Memory 11.13 Asynchronous WRITE (CS Controlled) ADV VIH VIL tCVS tAVS VIH VIL VIH VIL VIH VIL VIH VIL tAW tAVS Data Valid Valid Address tCVP tAVH tAVS Valid Address tAVH A[22:16] Valid Address tCW tBSA tCPH tBHA CS UB/LB tWP WE A/DQ[15:0] VIH VIL tAVH Valid Address tAVS tAVH tDW tDH Don't Care NOTE : 1) Don't care must be in VIL or VIH. 2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. 3) tCW is measured from the CS going low to the end of write. 4) tAS is measured from the address valid to the beginning of write. 5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. - 118 K5N1229ACD-BQ12 datasheet (WE, UB/LB Controlled) tVS tVP tVP tWR tCVS tAVS tAVS Valid Address Rev. 1.0 MCP Memory 11.14 Asynchronous WRITE ADV VIH VIL tAVH tAVH A[22:16] VIH VIL VIH VIL VIH VIL VIH VIL Valid Address CS tCW tBSA tBHA UB/LB tWP tBHZ Data Valid WE tAW A/DQ[15:0] VIH VIL Valid Address tAVS Valid Address tAVH tAVS tAVH tDW tDH Don't Care NOTE : 1) Don't care must be in VIL or VIH. 2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. 3) tCW is measured from the CS going low to the end of write. 4) tAS is measured from the address valid to the beginning of write. 5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. - 119 K5N1229ACD-BQ12 datasheet tVS tVP tWR Rev. 1.0 MCP Memory (CS Controlled) 11.15 Asynchronous WRITE Followed by Asynchronous READ ADV VIH VIL tAVS A[22:16] VIH VIL tCVS Valid Address tAADV tAVH tVP Valid Address tCPH CS VIH VIL tCW tAVS tCVS tAVH tBSA VIH UB/ LB VIL tBHA tCO tBA tOE tHZ tBHZ VIH OE VIL tOLZ tWP WE VIH VIL tAW A/DQ[15:0] VIH VIL Valid Address Data Valid tOHZ tHZ Valid Address tAA VOH VOL Valid output tAVS tAVH tDW tDH tAVS tAVH Don't Care Undefined - 120 K5N1229ACD-BQ12 datasheet tVS tVP tWR Rev. 1.0 MCP Memory (OE, WE Controlled) 11.16 Asynchronous WRITE Followed by Asynchronous READ ADV VIH VIL tAVS A[22:16] VIH VIL tCVS Valid Address tAVH tVP Valid Address tAADV CS VIH VIL tCW tAVS tCVS tAVH tBSA VIH UB/ LB VIL tBHA tCO tBA tOE tHZ tBHZ VIH OE VIL tOLZ WE VIH VIL tAW Valid Address tOHZ tWP tBHZ Data Valid tAA Valid Address VOH VOL Valid output A/DQ[15:0] VIH VIL tAVS tAVH tDW tDH tAVS tAVH Don't Care Undefined - 121 K5N1229ACD-BQ12 datasheet tCLK tKP tKP tKHKL Rev. 1.0 MCP Memory 11.17 Burst WRITE Operation--Variable Latency Mode VIH VIL VIH VIL tSP tHD tAHCR tAVH A[22:16] VIH VIL VIH VIL tCSM CS VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL tCSW High-Z NOTE 2 CLK tKADV ADV Valid Address tSP tHD LB/UB tCSP tHD tCBPH OE tSP tHD WE tKHTL tHZ High-Z WAIT tSP A/DQ[15:0] tHD tSP tHD Valid Address D1 D2 D3 D4 WRITE Burst Identified (WE = LOW) Don't Care NOTE : 1) Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2) WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]). 3) Don't care must be in VIL or VIH. - 122 K5N1229ACD-BQ12 datasheet tCLK tKP tKP tKHKL Rev. 1.0 MCP Memory 11.18 Burst WRITE Operation--Fixed Latency Mode CLK VIH VIL VIH VIL tSP tHD tAHCR tAVH A[22:16] VIH VIL VIH VIL tCSM CS VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL tCSW High-Z NOTE 2 tKADV ADV Valid Address tSP tHD LB/UB tCSP tHD tCBPH OE tSP tHD WE tKHTL tHZ High-Z WAIT tSP tHD tSP tHD A/DQ[15:0] Valid Address D[1] D[2] D[3] D[4] WRITE Burst Identified (WE = LOW) Don't Care NOTE : 1) Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2) WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]). 3) Don't care must be in VIL or VIH. - 123 K5N1229ACD-BQ12 datasheet tCLK tKHKL tKP tKP Rev. 1.0 MCP Memory 11.19 4-Word Burst WRITE Operation - Row Boundary Crossing VIH VIL tSP ADV VIH VIL tAVS VIH A[22:16] VIL VIH LB/UB VIL tCSP CS VIH VIL VIH VIL tSP WE VIH VIL VOH VOL tSP A/DQ[15:0] IN/OUT VIH VIL tHD tSP VOH D1 D2 D3 D4 Valid Address CLK tHD tAHCR tSP tAVH A tHD tHD tCBPH OE tHD tCSW tHZ High-Z WAIT tHD High-Z Valid Address VOL WRITE Burst Identified (OE = HIGH) End of Row Don't Care Undefined NOTE : 1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) Don't care must be in VIL or VIH. 3) D2 can be written when CS goes high at Point A. 4) There is no limitation for CS high time during Row Boundary Crossing. 6) There is no ADV low during Row Boundary Crossing. - 124 K5N1229ACD-BQ12 datasheet tCLK Rev. 1.0 MCP Memory 11.20 Burst WRITE Followed by Burst READ, Variable Latency VIH VIL VIH VIL VIH VIL VIH VIL VIH CS VIL VIH OE VIL VIH WE VIL VOH VOL VIH VIL tSP tHD Valid Address CLK tSP tHD Valid Address tSP tHD Valid Address A[22:16] tSP tHD ADV LB/UB tAHCR tSP tHD tSP tHD tAHCR tSP tCBPH NOTE2 tCSP tHD tCSP tADVO tOHZ tSP tHD tSP tHD tCSW tSP tHD D0 D1 D2 D3 tCSW tSP tHD Valid Address tBOE High-Z WAIT VOH tACLK tKOH Valid Output Valid Output Valid Output A/DQ[15:0] Valid Output VOL Don't Care Undefined NOTE : 1) Non-default BCR settings for burst WRITE followed by burst READ: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2) A refresh opportunity must be provided every tCSM by taking CS HIGH. 3) Don't care must be in VIL or VIH. - 125 K5N1229ACD-BQ12 datasheet tCLK Rev. 1.0 MCP Memory 11.21 Burst WRITE Followed by Burst READ, Fixed Latency VIH VIL VIH VIL VIH VIL VIH VIL VIH CS VIL VIH OE VIL VIH WE VIL VOH VOL VIH VIL tCSW tSP tHD Valid Address CLK tSP tHD Valid Address tSP tHD Valid Address A[22:16] tSP tHD ADV LB/UB tAVH tAHCR tSP tHD tKADV tSP tHD tAVH tAHCR tSP tCBPH NOTE2 tCSP tHD tCSP tADVO tOHZ tSP tHD tSP tHD tCSW tSP tHD D0 D1 D2 D3 tBOE High-Z WAIT VOH VOL tSP tHD Valid Address tACLK tKOH Valid Output Valid Output Valid Output A/DQ[15:0] Valid Output Don't Care Undefined NOTE : 1) Non-default BCR settings for burst WRITE followed by burst READ: fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asseted during delay. 2) A refresh opportunity must be provided every tCSM by taking CS HIGH. 3) Don't care must be in VIL or VIH. - 126 K5N1229ACD-BQ12 datasheet Valid Address tAVS tVS tWR tVP tBW Rev. 1.0 MCP Memory 11.22 Asynchronous WRITE Followed by Asynchronous READ A[22:16] VIH VIL Valid Address tAVS tAADV ADV VIH VIL LB/UB VIH VIL tCVP VIH VIL VIH VIL VIH VIL tCSW tCSW tBSA tWP tBHA tCW tCPH tBA tHZ tCO tBHZ CS Note 1 tOLZ tOHZ OE tOE WE WAIT VOH VOL High-Z tAVS A/DQ[15:0] VIH IN/OUT VIL tAW tAVH tAA tDS tDH tAVS Valid Address Valid Input Valid Address VOH VOL Valid Output Don't Care Undefined NOTE : 1) CS can stay LOW when transitioning between asynchronous operations. If CS goes HIGH, it must remain HIGH for at least tCPH to schedule the appropriate internal refresh operation. 2) Don't care must be in VIL or VIH. - 127 K5N1229ACD-BQ12 datasheet Valid Address tAVS tVP tBA tBW tAADV Rev. 1.0 MCP Memory 11.23 Asynchronous READ Followed by WRITE at the Same Address A[22:16] VIH VIL ADV VIH VIL LB/UB VIH VIL VIH VIL VIH VIL VIH VIL tCSW High-Z tCPH tCVP tCO tOE tOHZ CS OE tOLZ tWHZ WE tWP NOTE2 WAIT VOH VOL tAA tAVS tAVH VOH VOL tDS tDH VIH VIL A/DQ[15:0] VIH IN/OUT VIL Valid Address Valid Output Valid Input Don't Care Undefined NOTE : 1) The end of the WRITE cycle is controlled by CS, LB/UB, or WE, whichever de-asserts first. 2) WE must not remain LOW longer than 2.5s (tCSM) while the device is selected (CS LOW). 3) Don't care must be in VIL or VIH. - 128 |
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